TD1205 vs SN65LVDS105PWR Comparación
Comparación detallada lado a lado de TD1205 por TD next y SN65LVDS105PWR por Texas Instruments. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Texas Instruments
SN65LVDS105PWR - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI
SN65LVDS105PWR ✓ ActivoComparación de especificaciones
| Parámetro | TD1205 | SN65LVDS105PWR |
|---|---|---|
| Marca | TD next | Texas Instruments |
| Categoría | RF Modules | Clock & Timing |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,50 | $1,28 |
| Product Type | Sigfox-certified RF transceiver module | — |
| Manufacturer | TD next (Telecom Design) | — |
| RF Protocol | Sigfox (Ultra-Narrow-Band LPWAN) | — |
| Operating Frequency (RC1) | 868 MHz (ETSI Europe) | — |
| Operating Frequency (RC2) | 902-928 MHz (US, Australia, Japan) | — |
| Tx Power (RC1) | +14 dBm typical | — |
| Tx Power (RC2) | +22 dBm maximum | — |
| Receiver Sensitivity | [DATA_NEEDED: receiver sensitivity] | — |
| Integrated Microcontroller | ARM Cortex-M0+ (STM32 family) | — |
| Clock Reference | Integrated TCXO | — |
| Host Interface | UART, SPI, I2C, GPIO | — |
| Modulation | Ultra-Narrow-Band (UNB), DBPSK uplink | — |
| Maximum Payload Size | 12 bytes per uplink message | — |
| Tensión de alimentación | [DATA_NEEDED: VBAT operating range] | 3 V to 3.6 V (typical 3.3 V) |
| Temperatura de funcionamiento | -40C to +85C | [DATA_NEEDED: operating temperature range] |
| Form Factor | Surface-mount LGA castellation module | — |
| Tipo de montaje | Surface Mount (reflow) | Surface Mount |
| Estado RoHS | Compliant | — |
| Función | — | 1 LVTTL input to 4 LVDS output repeater / fanout buffer |
| Velocidad de datos | — | 400 Mbps |
| Max Clock Frequency | — | 400 MHz |
| Input Type | — | LVTTL (single-ended) |
| Tipo de salida | — | LVDS (differential), 4 pairs |
| Output Voltage (typical) | — | 350 mV into 100 ohm load |
| Standard Compliance | — | ANSI EIA/TIA-644 LVDS |
| Canales | — | 1 x 1:4 |
| Encapsulado | — | 16-TSSOP (PW) |
| Technology | — | LVDS differential signaling |
| Categoría | — | Signal Buffers, Repeaters, Splitters - Clock Buffer |
| Corriente en reposo | — | [DATA_NEEDED: quiescent current] |
| Input Rise/Fall Time Note | — | TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance |