Integrierte Schaltungen

SI5332ED12635-GM2

SI5332ED12635-GM2 - 8-Output Any-Frequency Clock Generator | Skyworks

The Skyworks Solutions SI5332ED12635-GM2 is a low-jitter, embedded-crystal 8-output any-frequency clock generator housed in a 40-pin TFLGA exposed-pad package. It supports output frequencies up to 333.33 MHz using Skyworks' proprietary MultiSynth flexible frequency synthesis technology, and delivers typical RMS jitter of 0.175 ps while drawing low quiescent power from a 1.71 V to 3.63 V supply. The SI5332ED12635-GM2 is a factory-configured variant of the broader Si5332E family, programmed over I2C for specific frequency plans (the trailing "D12635" encodes the customer-specific output plan), and integrates an internal reference crystal so no external XTAL is required. An any-frequency clock generator is a high-performance timing IC that consolidates multiple oscillators and PLLs into a single chip, synthesizing independent output frequencies from one reference. Clock generators sit below XO/VCXO parts and above simple PLL multipliers in the timing hierarchy, and they belong to the broader class of frequency synthesizers and clock-management ICs that govern synchronous logic in communications, computing, and industrial systems. The "any-frequency" designation means each output channel can be set independently across the device's supported frequency range. Key features of the SI5332ED12635-GM2 include 8 differential or 16 single-ended outputs (configurable per bank), an internal 50 ppm reference crystal eliminating external frequency components, and typical RMS phase jitter below 200 fs (12 kHz to 20 MHz). The device supports I2C serial programming with non-volatile on-chip NVM storage, eliminating external configuration EEPROM. A wide 1.71 V to 3.63 V core supply range and industrial -40C to +85C operation suit embedded and outdoor applications. Each output bank supports individual format and voltage configuration. At the silicon level the Si5332E family uses a fractional-N MultiSynth architecture with per-output dividers, allowing non-integer frequency relationships without the integer-bound spurs of conventional PLL architectures. MultiSynth's fractional feedback reduces accumulated jitter, making the part attractive for 10/25/40/100G serial-link reference clocks, ADC/DAC sampling clocks, and FPGA/ASIC reference inputs where clean jitter translates directly into bit-error or aperture performance. Typical applications include 10/25/40/100G optical-module reference clocks, FPGA fabric and transceiver reference planes in networking line cards, industrial Ethernet switches and routers, broadcast video frame syncs, and test-and-measurement instrumentation timing backplanes. Each application benefits from the consolidated BOM and tight output-to-output skew the Si5332E family provides. When designing with this part, place the mandatory bulk-decoupling capacitors within 2 mm of the supply pins, and tie the exposed pad to a contiguous ground plane for thermal dissipation and low-inductance return paths. Because the device is factory-configured for a specific frequency plan, ensure the part's order code (e.g., D12635) matches the intended output map before PCB release. This page synthesizes distributor pricing, factory-configured order-code variants, package-aware drop-in alternatives, and PCB layout guidance that go beyond what is shown on a generic distributor product page.

USD $7,05 Auf Lager

SI5332FD10368-GM1R

SI5332FD10368-GM1R - 6-Output Any-Frequency Clock Generator | Skyworks

The Skyworks Solutions SI5332FD10368-GM1R is a low-jitter, any-frequency clock generator based on proprietary MultiSynth flexible frequency synthesis technology, packaged in a 32-pin QFN and specified for industrial-grade operation. The device synthesizes up to six independent output frequencies with typical 190 fs RMS phase jitter (12 kHz to 20 MHz) and supports any combination of integer and non-integer related output frequencies below 200 MHz. A clock generator is a semiconductor device that produces one or more precise reference timing signals from a single input reference (typically a crystal or external clock), and falls within the broader hierarchy of timing ICs -> clock generation -> clock and timing -> integrated circuit. Clock generators sit at the foundation of every digital system, providing the timing reference that drives processors, FPGAs, serializers, memory interfaces, and data converters. Compared with discrete oscillator trees, a single programmable clock generator replaces multiple crystals and oscillators while offering finer frequency resolution. Key differentiating features include an embedded crystal option, six independently configurable outputs, sub-200 fs RMS jitter, integrated LDOs that eliminate external supply rails, and I2C/SPI programmable configuration. Output formats include LVDS, LVPECL, HCSL, CML, and CMOS, making the Si5332 compatible with virtually any downstream logic. The 32-QFN package provides a compact 5x5 mm footprint suitable for high-density PCB designs. Architecturally, the Si5332 separates the reference input from the synthesis core via a low-noise PLL, then routes the synthesized frequency through six independent MultiSynth fractional dividers. Each output can be independently programmed for frequency, format, and slew rate through non-volatile on-chip memory or via the serial control interface at start-up. Typical applications include networking line cards, server and storage controllers, FPGA reference clocks, broadcast video systems, industrial automation, and any multi-rail digital platform that previously required multiple XO/VCXO components. When migrating from discrete oscillator trees, designers should budget for the I2C/SPI configuration EEPROM image and confirm jitter performance against the most stringent downstream serializer requirement.

USD $8,81 Auf Lager

SI5332H-D-GM1

SI5332H-D-GM1 - 6-Output Any-Frequency Clock Gen | Skyworks

The Skyworks Solutions SI5332H-D-GM1 is a low-jitter, 6-output any-frequency clock generator housed in a 32-pin QFN-EP (5x5 mm) package with embedded crystal and MultiSynth flexible frequency synthesis technology. It supports up to 200 MHz output frequencies (datasheet headline) with measured RMS jitter of 190 fs (per the Si5332 family datasheet), operating from a 1.8 V to 3.3 V core supply and providing individual VDDO pins per output. A clock generator is an integrated circuit that synthesizes one or more precise timing references from a single input reference, replacing multiple crystal oscillators and PLLs in a system. Within the broader silicon taxonomy it sits as: clock generator -> timing IC -> clock and timing subsystem -> power management and analog mixed-signal IC -> semiconductor. By consolidating multiple clock domains onto a single I2C-programmable device, the SI5332H-D-GM1 reduces BOM count, PCB area, and the long-term reliability risks of multi-crystal designs. Key features include any-frequency output synthesis on six differential or single-ended outputs, hardware configuration input pins for boot-time setup, per-output voltage domains (VDDO) for level translation, an I2C control interface, and integer (INT) divider support. Internal MultiSynth fractional dividers provide sub-Hz frequency resolution while maintaining low phase noise, and the integrated crystal reference eliminates an external timing component. Typical applications include 10/25/40/100G data center communications equipment, industrial Ethernet switches and routers, FPGA and ASIC reference clock trees, broadcast video timing, and any multi-rail system requiring jitter-clean fanout. The wide frequency range and flexible output formats make it a strong fit where multiple unrelated clock frequencies must be derived from a single reference. When designing with this device, place the bypass capacitors as close as possible to each VDDO pin to minimize output jitter degradation, and follow Skyworks' reference manual layout for the exposed pad to achieve the rated thermal performance. The I2C address is hardware-configurable via input pins, so plan address strapping early in the schematic. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the Skyworks datasheet PDF, with cross-references to the Si5332 family reference manual for register-level configuration details.

USD $14,95 Auf Lager

SI53340-B-GM

SI53340-B-GM - 1.25GHz LVDS 2:4 Clock Buffer | Skyworks

The Skyworks SI53340-B-GM is an ultra-low-jitter LVDS 2:4 fanout clock buffer with integrated glitchless input mux, delivering four LVDS outputs from a single LVDS reference up to 1250 MHz, packaged in a 16-pin QFN (3x3 mm) with exposed thermal pad. It features 50 fs typical additive jitter, 2.97 V to 3.63 V supply operation, and built-in LDOs providing high PSRR for low-jitter clock distribution in noisy environments. Key differentiators include the 2:1 glitchless switching input mux (reduces runt pulses and phase transients during reference switchover), four LVDS outputs that meet ANSI TIA/EIA-644 standards with complementary pairs, and a wide DC-to-1250 MHz input frequency range that supports both reference clocks and high-speed data. The device is specified across -40 °C to +85 °C industrial temperature range and integrates on-chip LDOs that reject supply noise without external filtering. The SI53340-B-GM uses Skyworks' advanced CMOS technology to guarantee 50 fs RMS typical additive jitter (12 kHz-20 MHz), 10 ps peak-to-peak output-to-output skew, and sub-picosecond propagation delay variability across process, voltage, and temperature. The integrated LDOs operate from a single 2.97 V-3.63 V supply and provide the analog blocks with a quiet internal rail, eliminating the requirement for an external clock-screened supply in most designs. Typical applications include redundant clocking in communications infrastructure (SONET/SDH, OTN, SyncE, GbE switches), high-speed serial backplane fanout (XAUI, PCIe, SATA, SAS), multi-card clock distribution in ATCA/uTCA platforms, professional broadcast video and audio reference clocking, and FPGA/ASIC reference distribution. The LVDS outputs are well suited for point-to-point and short-haul distribution of differential clocks on controlled-impedance PCB traces. When designing with this device, route LVDS traces as 100-Ω differential pairs with controlled impedance, keep output trace lengths matched within 150 mil to minimize skew across outputs, and decouple each VDD pin with a 0.1 μF ceramic capacitor placed within 2 mm of the pin. The exposed thermal pad must be soldered to a ground plane for electrical ground and thermal dissipation. The mux status output can be monitored to detect reference switchover events in redundant systems. This page synthesizes distributor pricing, drop-in alternatives, and practical layout guidance beyond the manufacturer datasheet.

USD $3,28 Auf Lager

SI5335B-B01461-GM

SI5335B-B01461-GM - 4-Output Any-Freq Clock Generator | Skyworks

The Skyworks Solutions (formerly Silicon Labs) Si5335B-B01461-GM is a web-customizable, any-frequency, any-output quad clock generator that synthesizes four completely non-integer-related frequencies between 1 MHz and 200 MHz on four independent output banks, housed in a 24-pin QFN (4x4 mm) exposed-pad package. A clock generator is a semiconductor device that produces one or more precise timing references from a single input frequency source, replacing multiple discrete oscillators to reduce BOM cost and board area. The Si5335B family belongs to the broader category of clock generators, frequency synthesizers, and phase-locked loops (PLLs) used in any electronic system that requires synchronized timing. By integrating a PLL with a fractional-N MultiSynth divider, the Si5335B can derive multiple unrelated output frequencies from a single low-cost external crystal, an architectural choice that simplifies supply chains versus stocking four discrete XOs. The Si5335B-B01461-GM provides four output banks, each of which can be configured as one differential pair or two single-ended CMOS clocks. Its core MultiSynth technology independently synthesizes each output, eliminating phase alignment between banks. Integrated configurable output drivers support LVDS, LVPECL, HCSL, CML, and CMOS swing levels, removing the need for external translator ICs. An I2C/SPI interface allows in-system reconfiguration of frequency and format. Power is drawn from a single 1.8V to 3.3V supply, and the device operates over the industrial -40C to +85C temperature range. Typical applications include general-purpose clock tree replacement, networking and telecom line cards, multi-processor and FPGA/ASIC reference clocks, test and measurement equipment, and PCIe timing fan-out. The compact 4x4 mm QFN footprint and high integration make the Si5335B-B01461-GM especially attractive in dense PCB designs where multiple clock sources would otherwise compete for board area. When designing with this part, use the free ClockBuilder Pro software to generate the exact frequency plan and register configuration for your project. Place the external 8-32 MHz crystal or reference input as close to the XIN/XOUT pins as possible to minimize jitter, and provide a solid ground plane under the exposed pad (EP) for thermal dissipation and return-path integrity.

USD $9,05 Auf Lager

SI5335B-B01955-GM

SI5335B-B01955-GM - 4-Output Any-Freq Clock Generator | Skyworks

The Skyworks SI5335B-B01955-GM is a 4-output, web-customizable differential clock generator in a 24-pin QFN (4x4 mm) package with exposed pad. It synthesizes up to 4 non-integer-related frequencies from 1 MHz to 200 MHz per output bank, with each bank supporting one differential pair or two single-ended CMOS outputs. The device uses Skyworks' MultiSynth fractional divider technology to achieve sub-100 fs RMS typical phase jitter on the differential outputs. What is a clock generator? A clock generator (or frequency synthesizer) is a timing IC that takes one or more reference inputs - typically a low-cost crystal or external oscillator - and produces one or more output frequencies, often at unrelated values, while preserving low jitter and tight frequency accuracy. Clock generators sit within the broader clock-and-timing hierarchy: crystal/oscillator -> clock generator/PLL -> frequency synthesizer -> clock distribution/buffer. They are essential building blocks in any digital system that needs multiple synchronized clocks, and the SI5335B integrates the entire PLL chain on-chip. Key features of the SI5335B include: 1.8 V core supply, 2.5 V or 3.3 V output supply for flexible level translation, 5 user-assignable control pins for output enable, frequency-plan selection, or PCIe-compliant spread-spectrum control, two selectable PLL loop bandwidths for jitter attenuation in PCIe and DSL applications, and integrated 50-ohm output terminations on differential banks. The custom frequency plan is stored in on-chip NVM configured via the ClockBuilder Pro web utility before shipment. Architecturally, the SI5335B combines a high-frequency integer PLL with four independent MultiSynth fractional dividers, allowing completely arbitrary per-output frequency ratios to the same reference - a feature that previously required multiple discrete PLLs and complex loop-filter design. Each output bank can be individually set to LVPECL, LVDS, HCSL, CML, or CMOS formats via ClockBuilder configuration, supporting legacy and modern SERDES interfaces in the same part. Typical applications include general-purpose clock-tree replacement, networking/communication line cards, server and storage PCIe reference clocks, industrial automation controllers, and consumer video/audio equipment that require multiple unrelated sample-rate clocks. The wide output-format support lets one part serve as a single BOM item across mixed-signal boards. When designing in this part, allocate a 25 mm x 25 mm PCB land pattern with a continuous ground plane beneath the exposed thermal pad - the pad is the primary heat-dissipation path and must be soldered to a top-side ground pour with at least four thermal vias to the inner/inner planes. Configure all frequency plans through ClockBuilder Pro at prototype release; field configuration is not possible without re-NVM programming.

USD $1,62 Auf Lager

SI5335B-B02199-GMR

SI5335B-B02199-GMR - 4-Output Any-Freq Clock Generator | Skyworks

The Skyworks SI5335B-B02199-GMR is a highly flexible 4-output any-frequency, any-output clock generator that synthesizes four completely non-integer-related frequencies up to 200 MHz using the manufacturer's patented MultiSynth fractional divider architecture. Housed in a 24-pin QFN-EP (4x4 mm) package, it accepts a single-ended crystal or reference input and delivers four independently programmable output banks, each supporting one differential pair or two single-ended CMOS clocks, guaranteed to have 0 ppm frequency synthesis error. What is a multi-output clock generator? A clock generator is a timing IC that replaces multiple crystal oscillators on a printed circuit board by deriving several unrelated output frequencies from one reference input, providing a small, low-jitter, factory-customized alternative to a bill of multiple XOs. The SI5335B sits within the broader hierarchy: clock generator -> clock synthesizer -> frequency synthesizer -> timing IC -> mixed-signal semiconductor. Modern programmable clock ICs let PCB designers consolidate BOM by ordering one factory-configured part that ships with a custom frequency plan, rather than placing four separate crystals. Key features include any-output frequency from 1 MHz to 200 MHz, an I2C/SPI programmable register set, integrated low-jitter MultiSynth fractional dividers, 1.8V core supply, and four output banks of LVCMOS/LVDS-compatible drivers. The MultiSynth architecture guarantees 0 ppm frequency error even at non-integer frequency ratios, eliminating the fractional spurs common in PLL-only solutions. Per datasheet, typical RMS period jitter is under 10 ps across the supported frequency range, and the part is qualified across the -40C to +85C industrial temperature range. The 4-bank / 4-output topology runs from an internal PLL that locks the reference input, typically a low-cost 25 MHz or 27 MHz crystal, then routes each output through its own MultiSynth fractional divider. This enables completely independent, non-related output frequencies on each bank, simplifying timing trees for FPGAs, ASICs, processors, and serializers that require unrelated domain clocks. The I2C interface allows in-system frequency reconfiguration for design prototyping or debug. Typical applications include FPGA/ASIC reference-clock trees in communications infrastructure, multi-rate serializer-deserializer (SerDes) reference planes, industrial routers and switches, storage controllers, and any board that previously required multiple fixed-frequency XOs at different frequencies. When designing in the SI5335B, leave at least 4 mm² of uninterrupted ground copper under the exposed pad to keep junction temperature within the industrial range, follow the layout guidelines in the Si5335 datasheet to maintain <12 ps period jitter, and use an XTAL stage that follows the load-capacitor formula provided in the reference design. This page synthesizes distributor stock, Skyworks datasheet specifications, drop-in alternative Skyworks family parts, and PCB layout notes that simplify bring-up versus the bare datasheet alone.

USD $3,69 Auf Lager

SI5335B-B02699-GMR

SI5335B-B02699-GMR - 4-Output Any-Frequency Clock Generator | Skyworks

The Skyworks (formerly Silicon Labs) SI5335B-B02699-GMR is a web-customizable, any-frequency, any-output quad clock generator that synthesizes up to four independent non-integer-related frequencies between 1 MHz and 200 MHz on each output bank. Housed in a 24-pin QFN (4x4 mm) package, the device uses low-power MultiSynth technology to provide four independent fractional dividers, configurable as a clock generator or clock buffer, and supports both differential and single-ended output formats. A clock generator is a mixed-signal IC that produces one or more reference timing signals from a single input source (typically a crystal or reference clock). It is a sub-category of frequency synthesizers and timing ICs, sitting hierarchically under clock and timing > clock generator > frequency synthesizer > timing IC > power management / mixed-signal IC. Clock generators are essential building blocks in digital systems, providing synchronized timing to processors, memory, transceivers, ADCs/DACs, and serial links. The SI5335B sits in the high-performance tier of this hierarchy, offering drop-in multi-rate programmability that older integer-divider parts cannot match. Key features include 200 MHz maximum output frequency per output, sub-200 fs RMS phase jitter (12 kHz to 20 MHz integration), I2C/SPI serial configuration, two selectable PLL loop bandwidths (low and medium), and five user-assignable pin-selectable control inputs supporting output enables, frequency plan selection, spread-spectrum (PCIe) control, and master reset. Each of the four output banks can drive one differential pair or two single-ended outputs. The architecture pairs an internal integer PLL/MultiSynth with a precision fractional feedback divider, providing frequency resolution below 1 ppm while preserving low jitter at any output frequency. Independent non-integer-related outputs eliminate the need for multiple oscillators on the board, reducing BOM cost and PCB area in multi-rate designs. Typical applications include multi-rate Ethernet switches, PCIe Gen 2/3 reference clocks, broadcast video equipment, FPGA/processor reference clock trees, test and measurement, and industrial control backplanes requiring multiple synchronized but unrelated frequencies. When designing with the SI5335B, route each output trace with controlled 100-ohm differential impedance for LVDS/LVPECL formats, and place the external reference crystal within 5 mm of the XA/XB pins to minimize parasitic capacitance that affects ppm accuracy. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that complement the Skyworks datasheet and reference schematic in the Si5335B reference design manual.

USD $5,05 Auf Lager

SI5335B-B03626-GM

SI5335B-B03626-GM - 4-Output Any-Freq Clock Generator | Skyworks

The Skyworks SI5335B-B03626-GM is a factory-customized 4-output any-frequency, any-output quad clock generator, factory-programmed to synthesize user-specified output frequencies (each up to 200 MHz) from a single crystal/CMOS reference input. Housed in a 24-pin QFN (4x4 mm) package, the B03626 order code defines specific output frequencies, output format (LVCMOS/LVDS/LVPECL/HCSL/CML), and pin configuration generated by Skyworks' ClockBuilder tool. A clock generator is a device that produces one or more precise timing signals from a reference source; in multi-protocol systems, multiple unrelated frequencies are required (e.g. for CPU, memory, and serializer/deserializer), which historically required multiple crystal oscillators. Any-frequency clock generators like the SI5335B consolidate this into one IC by using an internal PLL with fractional-N dividers, reducing BOM cost, board area, and supply current. Key features include: any-output frequency from 1 MHz to 200 MHz, four independently programmable output banks each with a differential pair or two single-ended outputs, a built-in PLL with loss-of-lock detection, spread-spectrum capability for EMI reduction, selectable I/O formats per bank, and pin-selectable frequency references. The integrated PLL eliminates the need for external loop-filter components in most configurations. The device uses MultiSynth fractional divider technology, allowing truly non-integer-related frequencies on each output without the accumulated jitter typical of cascaded integer PLLs. The B03626 variant is supplied with a factory-programmed configuration that meets deterministic phase-noise and jitter targets. Typical applications include communications line cards, networking switches, server motherboards, FPGA/ASIC reference clocks, broadcast video, industrial control, and test-and-measurement equipment where multiple unrelated clock domains must be generated from a single low-cost crystal. When designing in the SI5335B, the B03626 ordering code is the specific configuration file applied at the factory; identical silicon (SI5335B die) with different code suffixes carry different pin/frequency maps, so selection by exact code is required. Pinout, output format, and frequency plan must be cross-checked against the factory datasheet supplement before PCB layout is committed.

USD $5,02 Auf Lager

SI5335B-B03900-GMR

SI5335B-B03900-GMR - 4-Output Any-Frequency Clock Generator | Skyworks

The Skyworks Solutions (formerly Silicon Labs) SI5335B-B03900-GMR is a web-customizable, any-frequency, any-output quad clock generator capable of synthesizing four completely non-integer-related frequencies up to 200 MHz per output (350 MHz on newer revisions per datasheet), all from a single external crystal or reference input. The device uses Skyworks' patented MultiSynth fractional divider technology to guarantee 0 ppm frequency synthesis accuracy on every output. Housed in a 24-pin QFN-EP (4x4 mm) package with an exposed thermal pad, it supports four output banks where each bank delivers one differential pair or two single-ended clocks, giving designers four differential or eight single-ended timing references from a single IC. The 1.8 V core supply and configurable output voltages (1.8 V, 2.5 V, 3.3 V) simplify interfacing with downstream SerDes, FPGA, ASIC, and processor clocks. A clock generator is a timing IC that produces one or more precision reference frequencies from a single input reference, replacing multiple crystal oscillators and reducing BOM cost. The SI5335 family falls within the broader hierarchy of clock generators -> frequency synthesizers -> PLL-based timing ICs -> clock & timing semiconductors. Unlike fixed-frequency XOs, the SI5335B can be factory- or web-configured to deliver any combination of output frequencies, output formats (LVDS, LVPECL, HCSL, CMOS), and drive strengths, making it a universal replacement for up to four separate oscillators. Key features include sub-200 ps peak-to-peak output-to-output skew, integrated 50 ohm output termination options, per-bank output enable/disable control, and I2C/SPI host interface for in-system reconfiguration. The internal MultiSynth architecture eliminates the need for external loop filter components and supports glitchless output frequency changes. The 1.8 V core with separate VDDO banks for each output allows mixed-voltage designs where one bank drives 1.8 V LVDS logic while another drives 3.3 V LVPECL PHYs without level translators. Technical depth: the MultiSynth fractional-N architecture permits arbitrary frequency synthesis with no integer-multiple relationship constraint between outputs. Each MultiSynth block contains its own fractional divider and VCO, so changing one output frequency does not perturb the others. This independence is critical in systems where the application processor, memory controller, PHY, and fabric clocks must run at unrelated rates, eliminating the need for multiple oscillators and reducing board area by up to 80 percent versus discrete XO banks. Typical applications include FPGA/ASIC reference clock generation, networking switches and routers, server and storage backplanes, broadcast video timing, industrial test and measurement, and any multi-rail system that previously required four separate crystal oscillators. The wide output format support makes it equally suitable for legacy CMOS logic and modern LVDS SerDes interfaces. As a Skyworks ClockBuilder Pro configurable device, every orderable part number such as the B03900-GMR suffix encodes a specific factory-programmed frequency plan, but the silicon itself is identical across the family. Design consideration: the exposed pad (EP) on the QFN-24-EP package must be soldered to a sufficient ground copper pour for thermal dissipation and low-inductance ground return. Place the input reference crystal within 5 mm of the XIN/XOUT pins and follow the datasheet's four-layer reference layout for skew-critical applications. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.

USD $3,48 Auf Lager

SI5335B-B10210-GM

SI5335B-B10210-GM - 4-Output Any-Frequency Clock Generator | Skyworks

The Skyworks Solutions SI5335B-B10210-GM is a highly flexible 4-output clock generator housed in a 24-pin QFN package that synthesizes four completely non-integer-related frequencies up to 200 MHz per output. Each of the four output banks supports one differential pair or two single-ended clocks, and every output is guaranteed to have 0 ppm frequency synthesis accuracy thanks to the proprietary MultiSynth fractional divider architecture. The part is factory-customized with the order code defining the exact frequency plan and output format configuration for the application. A clock generator is a clock/timing IC that derives one or more output frequencies from a single reference source. Clock generators integrate a phase-locked loop (PLL) and frequency dividers so that multiple independent clocks can be produced from a common reference, eliminating the need for multiple crystals across a board. Within the broader timing taxonomy, clock generators sit alongside clock buffers, PLL frequency synthesizers, and oscillators as one of four major timing-IC families; the SI5335 specifically targets applications where multiple unrelated clock frequencies are needed and absolute frequency accuracy is critical. Key features of the SI5335B-B10210-GM include support for any output frequency under 200 MHz, any output format (LVDS, LVPECL, HCSL, CMOS, SSTL), independent 1.5/1.8/2.5/3.3 V output bank supplies, and I2C/SPI programmable output skew and format. The MultiSynth architecture eliminates jitter degradation when fractional frequency conversions are performed, unlike traditional PLL-plus-divider implementations. A built-in crystal input stage accepts an external reference crystal, and the device supports multiple reference inputs and automatic switching for redundancy. Typical applications include multi-rate telecom line cards, FPGA/ASIC reference clocking, broadcast video equipment, industrial timing backplanes, networking switches/routers, and any high-density board replacing multiple crystals with a single programmable generator. The independent output bank supplies allow direct connection to ASICs with mixed-voltage I/O without level translation. When designing with this part, treat the order code as fixed for the lifecycle of the design - the SI5335B is factory-customized rather than user-reprogrammable at runtime, so the output configuration must be specified up front using the Skyworks ClockBuilder Pro tool. Decoupling must be placed on every bank supply pin to meet the output jitter specification.

USD $8,50 Auf Lager

SI5335C-B-GM

SI5335C-B-GM - 4-Output Any-Freq Clock Generator (<350 MHz) | Skyworks

The Skyworks Solutions (formerly Silicon Labs) SI5335C-B-GM is a web-customizable, any-frequency, any-output quad clock generator housed in a 24-pin QFN package. The base part number SI5335C-B-GM identifies the unprogrammed factory default configuration; the full ordering code is completed with a customer-specific 5-digit frequency code at the -B suffix. The device synthesizes four non-integer-related output frequencies between 1 MHz and 350 MHz and supports any mix of differential (LVPECL, LVDS, HCSL) or single-ended (LVCMOS, SSTL) output formats from a single device. A clock generator (also called a frequency synthesizer or clock generator IC) is a timing IC that produces one or more reference-grade output clocks from a single input reference, replacing multiple crystal oscillators and reducing BOM cost in systems that previously required separate XOs for each frequency. Modern quad clock generators with MultiSynth fractional dividers extend this concept by allowing all four outputs to run on independent, non-integer-related frequencies, eliminating frequency-planning restrictions at the architecture stage. Key features of the Si5335C family include a frequency range of 1 MHz to 350 MHz per output, sub-200 fs RMS phase jitter (12 kHz to 20 MHz), four independent MultiSynth fractional divider blocks, and five user-defined pins (3, 5, 6, 12, 19) selectable via the ClockBuilder utility. The 24-pin QFN package has a small 4x4 mm footprint and supports storage temperatures from -65 °C to +150 °C. Internally the Si5335C uses a PLL locked to a 2.5–50 MHz external reference, followed by Skyworks' patented MultiSynth fractional-N divider architecture that provides 0 ppm frequency synthesis error on every output independently. Per-bank supply pins (3.3 V, 2.5 V, 1.8 V, 1.5 V) mean each output bank can drive a different logic level without level translators, simplifying multi-format designs. Typical applications include telecom and networking line cards, multi-rate Ethernet PHYs, FPGA and processor reference clocks, PCIe Gen 2/3 reference generation, and broadcast video equipment where multiple unrelated frequencies must coexist. Per the manufacturer, the part is supplied in an industrial temperature grade. When designing in the Si5335C, drive the device with a clean external crystal or CMOS reference and use Skyworks' ClockBuilder desktop utility to generate the per-order factory-programmed NVM image before submitting your unique B-suffix code. Per the datasheet, output format, output enable polarity, and I²C address are configured via the B-code, not by external strapping. This page synthesizes distributor pricing, drop-in B-code ordering variants, and practical ClockBuilder workflow notes that supplement the manufacturer datasheet.

USD $4,75 Auf Lager

SI5335C-B02329-GMR

SI5335C-B02329-GMR - Quad Clock Generator <350MHz, 24-QFN | Skyworks

The Skyworks Solutions (formerly Silicon Labs) SI5335C-B02329-GMR is a web-customizable, any-frequency, any-output quad clock generator housed in a 24-pin QFN (4x4 mm) exposed-pad package. It synthesizes four completely non-integer-related frequencies up to 350 MHz with 0 ppm frequency synthesis accuracy using Skyworks' patented MultiSynth fractional divider technology. A clock generator is a semiconductor device that produces one or more periodic reference signals used to synchronize digital logic, data converters, communications PHYs, and microcontrollers. Clock generators sit within the broader clock and timing hierarchy: clock generator -> timing IC -> clock & timing -> integrated circuit. They typically replace multiple crystal oscillators (XOs) and provide frequency flexibility through I2C/SPI configuration, with sub-ps jitter performance when designed correctly. Key features of the SI5335C-B02329-GMR include four output banks supporting one differential pair or two single-ended outputs each (eight single-ended outputs maximum), a wide 0.16 to 350 MHz output frequency range per bank, configurable input reference (crystal, CMOS, differential), and per-output enable and frequency programming via the Skyworks ClockBuilder Pro software. The 24-QFN exposed-pad package provides low thermal resistance (theta-JA approximately 38 C/W) and a small PCB footprint suitable for space-constrained designs. At the architectural level, the device combines a low-noise integer PLL front end with four independent MultiSynth fractional output dividers. The PLL multiplies the reference frequency to an internal VCO rate, and each MultiSynth block further divides and fractionalizes this to produce arbitrary output frequencies without requiring external VCXO tuning. Internal regulators supply clean core power, and the I2C interface supports in-system configuration without hardware strapping. Typical applications include FPGA clock trees (Xilinx 7-series, Intel Cyclone), communications line-card timing, multi-rate ADC/DAC sampling clocks, server/storage backplane reference generation, broadcast video reference timing, and industrial control backplanes. The ability to derive four independent outputs from a single reference reduces BOM cost and PCB area versus discrete XO solutions. When designing with the SI5335C, place the input reference and load capacitors close to the XIN/XOUT pins, route each output to its load with controlled impedance and short traces, and connect the exposed pad to a solid ground pour for thermal dissipation. Decouple each VDD pin with 0.1 uF plus 1 uF ceramic capacitors placed as close as physically possible to the IC. This page synthesizes real distributor pricing, true drop-in pin-compatible Si5335 family variants, and practical PCB layout guidance not consolidated in the manufacturer datasheet alone.

USD $3,02 Auf Lager

SI5335C-B07520-GM

SI5335C-B07520-GM - 4-Output Clock Generator, 350 MHz, QFN-24 | Skyworks

The Skyworks (formerly Silicon Labs) SI5335C-B07520-GM is a web-customizable, any-frequency, any-output quad clock generator housed in a 24-pin QFN (4x4 mm) exposed-pad package. The device synthesizes four completely non-integer-related output clocks up to 350 MHz from a single reference input, with each of four output banks supporting either one differential pair or two single-ended CMOS outputs. Per the Skyworks Si5335 datasheet, frequency plans are factory-customized via the ClockBuilder Pro utility, and the on-chip MultiSynth fractional dividers eliminate the need for external VCXOs or crystal oscillators for most frequency plans. A clock generator IC (also called a frequency synthesizer or clock multiplier) is a timing device that derives one or more precise output frequencies from a single low-frequency reference source such as a crystal or oscillator. Within the broader IC taxonomy it sits under Clock & Timing ICs -> Clock Generator -> Timing IC -> Power Management and Signal Chain IC. Modern clock generators like the Si5335 family integrate PLLs with fractional-N dividers (MultiSynth) to produce arbitrary non-integer-related frequencies without the spurs typical of integer-N synthesizers, replacing legacy solutions built from discrete PLL + VCXO + divider chains. Key differentiating specifications include four independently-programmable output banks, output frequency range of 1 MHz to 350 MHz, low typical RMS phase jitter of sub-ps on select frequencies, integrated 2.5 V or 3.3 V LDO regulators permitting single 1.8 V / 2.5 V / 3.3 V supply operation, and five user-defined pins (pins 3, 5, 6, 12, 19) that the ClockBuilder Pro utility can customize for functions such as OE, FS, SS, PD, or frequency select. The exposed thermal pad of the QFN-24 package provides a low theta_JA thermal path for reliable operation across -40C to +85C ambient. The IC also features configurable spread-spectrum capability for EMI mitigation in consumer and industrial designs. The Si5335C architecture pairs a high-frequency integer PLL with four independent MultiSynth fractional output dividers, allowing each output to have a unique frequency unrelated to the others by any integer ratio. This is critical for systems that require CPU clock, DDR memory clock, PCIe reference clock, and an audio or video clock from a single device. The internal LDOs isolate the analog PLL supply from the noisy digital output supply, contributing to the part's strong jitter performance. Typical applications include networking switches and routers, FPGA-based designs (Xilinx 7-series, Intel Cyclone, Lattice ECP5), telecom base-station timing, multi-rate audio/video broadcast equipment, server and storage controller boards, and test-and-measurement instrumentation. When laying out the Si5335C, place the reference input crystal or LVCMOS source within 5 mm of the REF input pin, route each differential output pair with matched 100 ohm differential microstrip or stripline, and stitch the exposed pad with at least 9 thermal vias for low ground impedance. The datasheet recommends 0.1 uF decoupling close to each VDD pin and a 1 uF bulk capacitor near the exposed pad. This page consolidates distributor pricing, drop-in alternatives, and PCB design notes not found in a single point in the manufacturer datasheet.

USD $4,05 Auf Lager

SI5338A-B-GM

SI5338A-B-GM - 710MHz Any-Frequency Clock Generator, 24-QFN | Skyworks

The Skyworks SI5338A-B-GM is a high-performance, low-jitter I2C-programmable any-frequency clock generator capable of synthesizing independent frequencies on each of four output drivers up to 710 MHz, packaged in a 24-pin 4x4 mm QFN with exposed pad. It accepts an input reference from 5 MHz to 710 MHz and generates four independently programmable outputs with 0 ppm synthesis precision using Skyworks' patented MultiSynth technology, replacing up to four discrete crystal oscillators on a single 24-QFN footprint. A clock generator is a timing integrated circuit that produces one or more precise reference frequencies from a single input reference, eliminating the need for multiple crystal oscillators. Clock generators sit hierarchically under timing ICs, which in turn belong to the broader category of power management and clock tree devices. Modern any-frequency clock generators use fractional-N or digital PLL architectures to synthesize non-integer output frequencies without needing custom quartz crystals, dramatically simplifying BOM and sourcing for multi-protocol designs. Key features of the SI5338A-B-GM include an input reference range of 5 MHz to 710 MHz, four independently configurable outputs from 0.16 MHz to 710 MHz, typical RMS jitter below 0.7 ps (12 kHz to 20 MHz), an I2C control interface with on-chip non-volatile EEPROM for stand-alone configuration, and selectable output formats including LVDS, LVPECL, HCSL, CMOS, and SSTL. Supply voltage is 2.97 V to 3.63 V for the core, with separate output driver supplies at 1.71 V to 1.98 V or 2.25 V to 2.75 V. The device uses a digital PLL architecture with MultiSynth fractional dividers, allowing truly arbitrary frequency synthesis without the classic fractional-N spurs. Internal loop bandwidth and jitter attenuation are user-tunable via I2C registers, enabling optimization for both OCXO-referenced telecom systems and crystal-referenced Ethernet or PCIe applications. The 24-QFN exposed pad provides a thermal resistance of approximately 38 C/W, supporting industrial-grade operation from -40C to +85C. Typical applications include Ethernet switch and PHY clocking, Fibre Channel and PCIe reference clocks, telecom timing cards with SONET/SDH or SyncE hierarchies, and multi-protocol FPGA or processor clock trees. Industrial test equipment and broadcast video systems also benefit from the four independent outputs on a single footprint. When designing with this device, place the input reference crystal or oscillator within 5 mm of the REF pin and route the REF clock trace over a continuous ground plane to minimize jitter. The exposed pad must be soldered to a continuous ground plane with at least 16 thermal vias for proper heat dissipation and electrical performance. This page synthesizes distributor pricing from DigiKey and Mouser, drop-in alternatives in the same 24-QFN package, and practical design notes not found in the manufacturer datasheet. Engineers searching for SI5338A-B-GM datasheets, pinouts, pricing, and cross-references will find consolidated technical information optimized for component selection.

USD $8,50 Auf Lager

SI5338C-A-GM

SI5338C-A-GM - I2C Clock Generator, 200MHz, 4-Output | Skyworks

The Skyworks (formerly Silicon Labs) SI5338C-A-GM is an I2C-programmable, any-frequency, any-output quad clock generator IC delivering up to 200 MHz on four differential outputs from a single 24-pin QFN (4x4 mm) package. It uses proprietary MultiSynth fractional-N divider technology to synthesize four independently programmable output frequencies, replacing multiple crystal oscillators and complex discrete PLLs. The device operates from a 2.5 V / 3.3 V core supply plus an independent output supply rail. A clock generator (or frequency synthesizer) is a timing IC that produces one or more precise reference frequencies derived from a single input reference, typically a low-cost crystal or crystal oscillator. It belongs to the broader category of clock and timing ICs, which also includes buffers, multiplexers, jitter cleaners, and phase-locked loops (PLLs). In modern digital systems, clock generators sit at the top of the timing tree and feed downstream PHYs, SoCs, FPGAs, and memory controllers, so their jitter and frequency accuracy directly bound the performance of the entire board. Key features include any-frequency synthesis from 0.16 MHz to 200 MHz on each output, sub-200 fs RMS typical phase jitter (12 kHz to 20 MHz), four differential output drivers that can also be configured as eight single-ended CMOS clocks, I2C control interface for in-circuit reconfiguration, and a field-programmable variant via the Si5338/56-PROG-EVB. Independent output voltage rails (1.8 V, 2.5 V, or 3.3 V) eliminate level shifters when driving mixed-voltage logic. Architecturally, the Si5338C-A-GM integrates a low-noise integer-N PLL plus four independent MultiSynth fractional-N divider blocks, each with its own output driver. This dual-stage design achieves the wide frequency range of fractional synthesis while keeping the jitter contribution of the dividers low. The I2C interface exposes a 364-byte configuration RAM that the host can rewrite at any time, allowing in-system frequency changes for FPGA bitstream reconfiguration or link-rate switching. Typical applications include Ethernet switch PHY clocking (10/100/1G/10G), PCI Express Gen 1/2/3 reference clocks, Fibre Channel port timing, telecom line cards, FPGA fabric and transceiver reference clocks, and any system that needs multiple independent frequencies from one crystal reference. The 24-QFN (4x4) footprint is friendly to compact router and switch designs. When designing with this part, place the input reference crystal within 5 mm of the XIN/XOUT pins and route the output traces with controlled 50 ohm impedance. Verify the in-circuit I2C configuration script against your board's frequency plan before bringing up the system, since a wrong MultiSynth setting will appear as an output stuck at the wrong rate. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone Si5338 datasheet.

USD $4,65 Auf Lager

SI5338K-B-GM

SI5338K-B-GM - 4-Output I2C Clock Generator 0.16-710 MHz | Skyworks

The Skyworks Solutions SI5338K-B-GM is an I2C-programmable any-frequency, any-output quad clock generator housed in a 24-pin QFN (4x4 mm) package, capable of synthesizing four completely non-integer-related frequencies between 0.16 MHz and 710 MHz. The device targets Ethernet, Fibre Channel, PCI Express (PCIe), and Telecom reference-clock applications where multiple unrelated output frequencies must be generated from a single low-cost reference. A clock generator IC is a timing device that synthesizes one or more output reference clocks from a single input reference or crystal, multiplying, dividing, or translating the input frequency into the user-required outputs. Clock generators belong to the broader category of clock and timing ICs, which also includes clock buffers, PLL clock drivers, and jitter cleaners; they are the foundational timing building blocks of nearly every digital system that requires synchronous logic. Key features of the Si5338K include four output banks (each bank supporting one differential pair or two single-ended outputs), per-bank output enable control, I2C control of frequency and format, integrated MultiSynth fractional dividers, low RMS phase jitter, and a single OEB pin that can disable all outputs simultaneously. The Skyworks datasheet confirms operation from a 2.5 V / 3.3 V core supply and supports LVCMOS, LVDS, HCSL, and CML output formats from independently configured banks. Architecturally the Si5338K uses a wide-range MultiSynth fractional divider stage per output, allowing the four outputs to be completely independent and non-integer-related without requiring multiple external oscillators. This single-chip architecture replaces up to four discrete XOs or VCXOs, reducing BOM cost and PCB area on Ethernet switches, PCIe add-in cards, and storage controllers. Typical applications include Ethernet switch/router reference clocks, Fibre Channel SAN HBAs, PCI Express Gen 2/3 endpoint and root-complex reference clocks, telecom line cards, FPGA and ASIC reference-clock trees, and industrial test equipment. The device is also used as a low-jitter replacement for multiple crystal oscillators on dense motherboards. When designing with the Si5338K-B-GM, ensure that the input reference (crystal or LVCMOS) meets the datasheet frequency and stability requirements, and that the I2C pull-ups are sized for the bus capacitance. Decouple VDD pins with 0.1 uF and 10 uF capacitors placed as close as possible to the package, and respect the exposed-pad soldering guidelines for the 24-QFN thermal pad. This page synthesizes distributor pricing from DigiKey, Mouser, Arrow, and Octopart, drop-in Skyworks same-family alternatives already in production, and practical PCB-level design notes that go beyond the manufacturer datasheet.

USD $4,85 Auf Lager

SI5340A-B05364-GM

SI5340A-B05364-GM - 4-Output Ultra-Low Jitter Clock Generator | Skyworks

The Skyworks Solutions SI5340A-B05364-GM is an ultra-low jitter, 4-output, any-frequency, any-output clock generator housed in a 44-pin QFN (QFN-44) package with exposed thermal pad. It supports output frequencies up to 1028 MHz using Skyworks' MultiSynth fractional divider technology and delivers typical phase jitter of 90 fs (12 kHz to 20 MHz) for high-performance timing applications. What is a clock generator? A clock generator is an integrated circuit that produces one or more reference timing signals used to synchronize digital logic, serializers/deserializers, analog-to-digital converters, and digital-to-analog converters within a system. Clock generators sit higher in the timing hierarchy than simple oscillators because they accept a low-frequency reference (crystal or LVCMOS) and synthesize multiple independent output frequencies through fractional-N and integer-N phase-locked loops (PLLs). High-performance variants such as the Si5340A target jitter-sensitive applications like 100G/400G optical modules, broadcast video, and wireless baseband where sub-100 fs RMS jitter is mandatory. The SI5340A-B05364-GM supports up to 4 differential or LVCMOS outputs, 4 reference inputs, and provides both integer and fractional frequency synthesis modes for sub-Hz resolution. It operates from a 1.8V core supply and 3.3V I/O supply with typical quiescent current in the 200-300 mA range. The part integrates internal LDOs, non-volatile EEPROM for stand-alone configuration, and Skyworks' ClockBuilder Pro software for register map generation. Typical applications include 10G/25G/100G Ethernet PHY clocking, FPGA transceiver reference clocks, audio/video broadcast reference timing, and wireless infrastructure baseband DSP clocks. The 44-pin QFN package provides an exposed pad for thermal dissipation at high MultiSynth update rates. Designers should use Skyworks' ClockBuilder Pro to generate the configuration header before EEPROM programming, and verify the I2C/SPI serial interface pinout against the latest Si5341/40 Rev D datasheet family reference manual. Decoupling on VDD and VDDA must use low-ESR ceramic capacitors placed within 3 mm of the supply pins. This page synthesizes distributor pricing, drop-in alternatives from the same Skyworks Si5340/Si5341 family, and practical design notes not consolidated in the manufacturer datasheet. Pricing reflects distributor breaks as of 2026-10-10 and is subject to change.

USD $9,85 Auf Lager

SI5340A-D-GM

SI5340A-D-GM - 1028 MHz Ultra-Low Jitter 4-Output Clock Gen | Skyworks

The Skyworks (formerly Silicon Labs) SI5340A-D-GM is an ultra-low-jitter, any-frequency, any-output clock generator that synthesizes up to four differential or single-ended clocks up to 1028 MHz from a single reference input. Housed in a 44-pin 7x7 mm QFN package with exposed pad, the device combines a wide-band PLL with proprietary MultiSynth fractional divider technology to deliver 0.09 ps RMS phase jitter (12 kHz to 20 MHz) while consuming roughly 300 mW from a 1.71 V to 3.47 V supply. The -D ordering code denotes the 4-output variant of the Si5340 family (the Si5341 ships with 10 outputs). A clock generator is a mixed-signal IC that takes one or more reference clocks and produces one or more output clocks at arbitrary frequencies, often with finer frequency resolution than integer PLLs. In the timing hierarchy, the Si5340A sits above fixed-frequency crystal oscillators and below application-specific clock trees - it provides the low-jitter, programmable fan-out that backplanes, FPGAs, SoCs, and high-speed data converters require. MultiSynth technology performs integer and fractional frequency synthesis simultaneously, allowing non-integer output-to-input ratios without the spurious sidebands of classical fractional-N PLLs. Key features of the Si5340A-D-GM include four reference inputs (LOS) for hitless switching and holdover, per-output frequency and format programming, an I2C/SPI control port, and integrated LDOs that allow direct operation from a single 1.8 V, 2.5 V, or 3.3 V rail. The device supports LVPECL, LVDS, HCSL, CMOS, and CML output formats with per-output swing and termination control. Internal non-volatile memory stores the default frequency plan so the device boots into a known configuration without host intervention. Typical applications include 100G/400G Ethernet line cards, OTN/SONET/SDH equipment, FPGA and ASIC reference clock trees, broadcast video, test and measurement, and wireless baseband timing. The 0.09 ps jitter floor enables compliance with the strictest 25G/50G SerDes reference clock masks. When designing with the Si5340A-D-GM, follow Skyworks' CBPro clock-builder tool to generate the frequency plan and register settings; this avoids manual register tuning and guarantees datasheet jitter performance. Provide a clean 1.8 V or 2.5 V supply with adequate decoupling on each power pin and stitch the exposed paddle to a low-impedance ground plane for thermal and EMI performance. The SI5340A-D-GM is the production-programmed default-config 4-output version of the Si5340A family. Order code suffixes (e.g. -D09650) denote factory-programmed custom frequency plans; users can also program the device in-circuit over I2C. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving engineers a single reference for sourcing and second-sourcing the SI5340A-D-GM.

USD $14,75 Auf Lager

SI5340B-B-GM

SI5340B-B-GM - 350MHz 4-Output Ultra-Low-Jitter Clock Generator

The Skyworks Solutions SI5340B-B-GM is an ultra-low-jitter, four-output clock generator with a maximum output frequency below 350 MHz, four reference inputs, and phase jitter of 0.09 ps. It is packaged in a 44-pin VFQFN with an exposed pad and uses MultiSynth technology for integer or fractional frequency synthesis. The -B suffix identifies the B-series ordering option, while -GM denotes the specified package and configuration. A clock generator is an integrated timing device that accepts one or more reference inputs and produces multiple synchronized or independently synthesized output clocks. Clock generators are part of the broader clock-and-timing IC hierarchy, alongside PLLs, dividers, buffers, jitter cleaners, and oscillators. They simplify designs requiring multiple related frequencies while reducing the number of separate clock sources and distribution components. Key features of the SI5340B-B-GM include four outputs, operation up to 350 MHz, integer and fractional synthesis modes, four reference inputs, and low phase jitter of 0.09 ps. These characteristics suit communication infrastructure, network equipment, servers, test and measurement systems, and high-speed digital systems. The product family is described by Skyworks as an ultra-low-jitter, any-frequency, any-output generator designed for exacting performance requirements. The device architecture combines clock synthesis and distribution functions, allowing multiple output frequencies to be generated from selected references. This supports clock trees that require deterministic phase relationships and low noise. A 350 MHz maximum output enables the part to address high-speed interfaces and processor-related timing needs, although the actual usable frequency depends on configuration, reference input, output divider settings, and device specifications. Typical applications include networking and telecom line cards, data-conversion systems, optical transport equipment, FPGA clock trees, server timing, and high-end instrumentation. For these systems, the 0.09 ps phase-jitter figure can help preserve timing margin where reference-clock quality and downstream receiver requirements are stringent. The four-output architecture also allows clock distribution to multiple circuit blocks without using four unrelated oscillators. PCB design should preserve short, controlled-impedance clock routes, provide clean return paths, and keep sensitive clock inputs away from noisy power and switching nodes. The exposed thermal pad requires proper thermal design and a low-impedance connection to ground. Decoupling and layout recommendations must be confirmed against the current manufacturer datasheet and reference design. This page consolidates the verified manufacturer and distributor information, package details, application guidance, cross-reference findings, and practical engineering notes for the SI5340B-B-GM. It is intended to support clock-tree design, source comparison, procurement evaluation, and PCB implementation for timing-sensitive electronic systems.

USD $15,67 Auf Lager

SI5341A-B04995-GM

SI5341A-B04995-GM - 10-Output Ultra-Low Jitter Clock Generator | Skyworks

The Skyworks SI5341A-B04995-GM is an ultra-low jitter, any-frequency, any-output clock generator providing up to 10 differential or CMOS output clocks with output frequencies below 1028 MHz, housed in a 64-pin QFN exposed-pad (ePM) 9x9 mm package. Per the Si5341/40 family datasheet, this -B derivative integrates a custom frequency plan for the SI5341A-B04995-GM (a factory-programmed base part with a 49.495 MHz related reference plan) and supports up to 4 reference inputs with input frequencies from 10 MHz to 750 MHz. A clock generator (also called a frequency synthesizer) is a timing IC that takes one or more low-jitter reference clocks and produces multiple independent output frequencies locked to those references. Clock generators sit in the timing hierarchy between reference oscillators (e.g., OCXO, TCXO, crystal) and downstream transceivers, ADCs, DACs, FPGAs and ASICs. Within the broader IC taxonomy, this part is a Clock/Timing IC, sub-category Clock Generator, PLL, Frequency Synthesizer, and is used wherever system-level jitter budget, channel-to-channel skew, and deterministic phase noise matter. Key differentiating specifications include 0.09 ps RMS phase jitter (12 kHz to 20 MHz, typical) per Skyworks product page, integer and fractional-N synthesis modes, independently configurable output formats (LVDS, LVPECL, HCSL, CMOS, CML), and per-output programmable dividers. The Si5341A family supports hitless input switching and holdover modes for redundant reference architectures used in synchronous Ethernet and OTN equipment. The architecture combines a MultiSynth fractional-N output stage with a high-frequency low-noise PLL, giving sub-ps jitter independent of output frequency choice. The -B04995-GM suffix encodes a factory-configured frequency plan that targets specific application reference trees; users with a different plan order the same -A or -D base part and re-program the NVM through ClockBuilder Pro. Typical applications include 100G/400G optical transport networking line cards, wireless base station radios, broadcast video routers, and FPGA/ASIC reference clocking on test and measurement platforms. Designers pair the Si5341A with Skyworks Si538x jitter cleaners or Si560x oscillators when an external reference is required. When designing with this part, allocate the exposed pad (ePM) for thermal and ground return paths, route differential outputs with 100-ohm controlled impedance, and program the device through ClockBuilder Pro to lock in the required frequency plan. Holdover and reference switching behavior must be validated against system-level MTIE/TEK masks.

USD $17,40 Auf Lager

SI5341A-D-GM

SI5341A-D-GM - 10-Output Any-Frequency Clock Generator | Skyworks

The Skyworks SI5341A-D-GM is a 10-output, any-frequency, any-output ultra-low jitter clock generator that synthesizes up to 1028 MHz on each of ten differential outputs, integrated in a 64-pin VFQFN (QFN) exposed-pad package. The device integrates a wide-band PLL front-end with proprietary MultiSynth fractional-divider technology to generate non-integer related frequencies with 0.09 ps RMS phase jitter (12 kHz to 20 MHz), making it one of the lowest-jitter clock ICs in its class. The Si5341A operates from 1.71 V to 3.47 V supply rails and accepts four reference inputs (LVCMOS, LVDS, LVPECL, HCSL). Outputs are independently configurable as LVDS, LVPECL, HCSL, LVCMOS, or SiLabs' proprietary format on a per-pin basis, and each output frequency is set independently in software via ClockBuilder Pro. A clock generator is a precision timing IC that accepts one or more low-frequency references (crystal, XO, or recovered clock) and synthesizes multiple clean, independent high-frequency output clocks for SoCs, FPGAs, ASICs, ADCs, DACs, and PHYs. The "any-frequency, any-output" architecture means each of the 10 outputs can be a different frequency and a different format without external loop filters, so a single Si5341A replaces multiple XO/VCXO parts. Key features include 0.09 ps RMS typical phase jitter, fractional-N synthesis (1 ppb resolution), independent per-output dividers, programmable output slew rates, output enable/format pins, hardware configuration via I2C/SPI, and field-upgradeable NVM. Hardware configurations are stored in on-chip non-volatile memory and applied at power-up, allowing fully autonomous boot without host intervention. The QFN-64 with exposed thermal pad provides thermal resistance suitable for the 1 W typical operating dissipation. The architecture combines a low-noise integer PLL reference path with MultiSynth fractional output stages that suppress fractional spurs below -75 dBc even at non-integer frequency plans. This enables clean clock trees in systems where reference and backplane frequencies are unrelated (100G/400G Ethernet, OTN, wireless baseband, JESD204B ADC/DAC clocks). Typical applications include 100G/200G/400G Ethernet switch and router timing, OTN/WDM optical transport clock generation, JESD204B/C SYSREF for high-speed ADC and DAC converters, FPGA and ASIC reference clock trees, wireless base-station fronthaul, and broadcast video reference distribution. The wide output frequency range (0.0001 MHz to 1028 MHz) covers virtually any timing requirement in modern high-speed serial systems. Each output supports independent format and frequency, so a single Si5341A can supply SYSREF, device clock, and reference clock to a JESD204B subsystem simultaneously while also driving a backplane SerDes at a different rate. This consolidation replaces a rack of XO crystals and fanout buffers and reduces BOM cost. When designing with the Si5341A, use Skyworks ClockBuilder Pro for prototype configuration and always order factory pre-programmed OPN variants (e.g., Si5341A-Dxxxx-GM) for production to lock the configuration as a one-time programmable NVM image.

USD $10,85 Auf Lager

SI5341A-D07228-GM

SI5341A-D07228-GM - 10-Output Ultra-Low Jitter Clock Gen | Skyworks

The Skyworks SI5341A-D07228-GM is a 10-output, any-frequency, any-output ultra-low-jitter clock generator housed in a 64-pin VFQFN exposed-pad (QFN-64) package. It provides up to 1.028 GHz output frequency per channel with industry-leading 90 fs RMS phase jitter (12 kHz–20 MHz), combining a wide-band PLL with proprietary MultiSynth fractional-N synthesizer technology. According to the Si5341/40 family reference manual, the part supports external crystal inputs from 25 to 54 MHz, differential clock inputs from 10 to 750 MHz, and LVCMOS clock inputs from 10 to 250 MHz. The device operates from a 1.71 V to 3.47 V supply and is configured through an I2C/SPI interface. An any-frequency, any-output clock generator is a programmable timing IC that synthesizes arbitrary integer and non-integer related frequencies from a single reference. It belongs to the clock generator hierarchy: clock generator -> PLL/synthesizer -> timing IC -> semiconductor. By replacing multiple crystal oscillators with one programmable device, it enables design flexibility, BOM consolidation, and reduced board area for complex multi-clock systems used in communications infrastructure, broadcast video, and high-speed data conversion. Key features include 90 fs RMS ultra-low jitter, ten independently programmable outputs, integrated MultiSynth fractional-N blocks, and built-in holdover capability. The Si5341A-D07228-GM operates from a 1.71 V to 3.47 V supply, offers selectable LVDS, LVPECL, HCSL, and LVCMOS output formats, and integrates an EEPROM for autonomous configuration. It supports Glitchless output muting and per-output phase adjustment, which simplifies PCB layout in dense multi-clock domains. Architecturally, the Si5341A-D07228-GM combines a wide-band integer PLL that locks to an external reference with up to five MultiSynth fractional divider blocks that each independently synthesize non-integer related output frequencies. This dual-stage architecture avoids the spurs typical of single-loop fractional-N synthesizers while keeping frequency flexibility. Register-only configuration uses an I2C or SPI serial interface, and optional non-volatile configuration via on-chip EEPROM allows standalone boot without a host controller. Typical applications include wireless base station timing, broadcast video reference clock generation, high-speed ADC/DAC sampling clocks, FPGA/ASIC reference and fabric clocks, OTN/SONET/SDH line cards, and server/storage timing. In all these roles, the Si5341A's 90 fs jitter preserves signal integrity in high-speed serial links and tight SNR budgets. When designing with this device, allocate a 64-pin 9 mm × 9 mm QFN footprint with a sufficient thermal via array under the exposed pad to keep junction temperature within range. A high-isolation multi-layer stack-up with split analog/digital ground is recommended because the part is sensitive to power-supply noise on the PLL supply rails. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that are not found in the manufacturer datasheet alone.

USD $18,92 Auf Lager

SI5341B-B-GM

SI5341B-B-GM - 350MHz 10-Output Clock Generator | Skyworks

Skyworks Solutions SI5341B-B-GM is an ultra-low-jitter, any-frequency clock generator with 10 differential outputs, a maximum output frequency of 350 MHz, and a 64-pin VFQFN exposed-pad package. The family accepts references up to 750 MHz and uses integer or fractional frequency synthesis to generate independent output frequencies. According to the verified product information, its phase jitter is 0.09 ps. A clock generator is a timing IC that converts one or more reference sources into multiple synchronized or independently synthesized clocks. The Si5341B belongs to the PLL clock-generator hierarchy: clock generator -> frequency synthesizer -> timing and clock-management IC. This architecture reduces the number of separate oscillators and distribution components required in communications, networking, industrial, and test systems. Principal features include 10 outputs, four reference inputs, integer and fractional synthesis modes, a 350 MHz maximum output, and 0.09 ps phase jitter. A search listing for the target order code also identifies a 1.71 V to 1.89 V supply range, while Arrow describes a 10 MHz to 750 MHz input and 350 MHz output range. These values make the device suitable for systems requiring multiple low-jitter clocks with flexible frequency relationships. Internally, the Si5341B family combines a wide-band phase-locked loop with MultiSynth fractional-synthesis technology. Integer and fractional modes allow designers to select clock frequencies that are integer- or non-integer-related to the references. Differential outputs can support high-speed links and clock-sensitive circuitry, while the fractional capability simplifies synthesis when a conventional integer divider cannot produce the required relationship. Typical uses include high-speed serial-interface clocking, optical transport modules, network equipment, industrial instrumentation, and semiconductor test systems. The 0.09 ps phase-jitter figure is particularly relevant where timing margin, data-eye closure, or reference-clock purity affects system performance. Engineers must still evaluate frequency-plan support, output logic levels, reference stability, and PCB thermal conditions for each specific configuration. For layout, place the exposed-pad connection and decoupling network exactly as directed by the manufacturer reference manual. The VFQFN package relies heavily on its thermal pad for heat spreading, so via stitching and uninterrupted ground or supply copper beneath the device are important. This page combines verified source data with explicitly marked data gaps rather than inferring unverified electrical limits. This product data adds practical interpretation of verified distributor pricing, package identity, family-level frequency synthesis, and replacement constraints. It distinguishes an orderable configuration from other Si5341B programming variants and avoids treating different frequency codes as unqualified drop-in replacements.

USD $19,03 Auf Lager

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