SI5340A-D-GM - 1028 MHz Ultra-Low Jitter 4-Output Clock Gen | Skyworks
Teilenummer: SI5340A-D-GM ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $23.5 | $23,50 |
| 10 | $21.2 | $212,00 |
| 100 | $18.65 | $1.865,00 |
| 500 | $16.4 | $8.200,00 |
| 1.000 | $14.75 | $14.750,00 |
SI5340A-D-GM Übersicht
A clock generator is a mixed-signal IC that takes one or more reference clocks and produces one or more output clocks at arbitrary frequencies, often with finer frequency resolution than integer PLLs. In the timing hierarchy, the Si5340A sits above fixed-frequency crystal oscillators and below application-specific clock trees - it provides the low-jitter, programmable fan-out that backplanes, FPGAs, SoCs, and high-speed data converters require. MultiSynth technology performs integer and fractional frequency synthesis simultaneously, allowing non-integer output-to-input ratios without the spurious sidebands of classical fractional-N PLLs.
Key features of the Si5340A-D-GM include four reference inputs (LOS) for hitless switching and holdover, per-output frequency and format programming, an I2C/SPI control port, and integrated LDOs that allow direct operation from a single 1.8 V, 2.5 V, or 3.3 V rail. The device supports LVPECL, LVDS, HCSL, CMOS, and CML output formats with per-output swing and termination control. Internal non-volatile memory stores the default frequency plan so the device boots into a known configuration without host intervention.
Typical applications include 100G/400G Ethernet line cards, OTN/SONET/SDH equipment, FPGA and ASIC reference clock trees, broadcast video, test and measurement, and wireless baseband timing. The 0.09 ps jitter floor enables compliance with the strictest 25G/50G SerDes reference clock masks.
When designing with the Si5340A-D-GM, follow Skyworks' CBPro clock-builder tool to generate the frequency plan and register settings; this avoids manual register tuning and guarantees datasheet jitter performance. Provide a clean 1.8 V or 2.5 V supply with adequate decoupling on each power pin and stitch the exposed paddle to a low-impedance ground plane for thermal and EMI performance.
The SI5340A-D-GM is the production-programmed default-config 4-output version of the Si5340A family. Order code suffixes (e.g. -D09650) denote factory-programmed custom frequency plans; users can also program the device in-circuit over I2C.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving engineers a single reference for sourcing and second-sourcing the SI5340A-D-GM.
Drop-in-Alternativen für SI5340A-D-GM – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit SI5340A-D-GM (gleiche Bauform und Footprint) – abweichend in Package, Number of Outputs, Function, Output Formats, Maximum Output Frequency.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
SI5340A-D-GMR
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
SI5340B-A-GM
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
SI5340B-B03918-GM
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
SI5340C-B-GMR
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
SI5340A-B05364-GM
✅ Drop-In✓ Auf Lager
$9.85 / Stück
Datenblatt ansehen →SI5340A-D09650-GM
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
SI5341A-B-GMR
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
SI5340A-D-GM Technische Daten
| Funktion | Clock generator, any-frequency, any-output |
| Anzahl der Ausgänge | 4 |
| Number of References | 4 |
| Maximum Output Frequency | 1028 MHz |
| Output Logic | LVPECL, LVDS, HCSL, CMOS, CML (per output) |
| Versorgungsspannung | 1.71 V to 3.47 V (core); 1.8 V / 2.5 V / 3.3 V typical |
| Phase Jitter (12 kHz to 20 MHz) | 0.09 ps RMS (typical) |
| Frequency Synthesis Modes | Integer and fractional (MultiSynth) |
| Control Interface | I2C / SPI |
| Output Enable / Disable | Per-output |
| Gehäuse | 44-pin QFN (7x7 mm) with exposed pad |
| Montageart | Surface Mount |
| Betriebstemperatur | -40 C to +85 C (industrial) |
| MSL-Level | 3 |
| RoHS-Status | Compliant |
| Family | Si5340 / Si5341 |
| Order Code Suffix | -D (4-output default frequency plan) |
| Manufacturer | Skyworks Solutions Inc. (formerly Silicon Labs) |
SI5340A-D-GM Pin-Konfiguration
| Pin 1 | IN0 — Differential reference clock input 0 |
| Pin 2 | IN0b — Complementary reference clock input 0 |
| Pin 3 | VDD — Core 1.8 V / 2.5 V / 3.3 V supply |
| Pin 4 | IN1 — Differential reference clock input 1 |
| Pin 5 | IN1b — Complementary reference clock input 1 |
| Pin 6 | VDD — Core supply |
| Pin 7 | IN2 — Differential reference clock input 2 |
| Pin 8 | IN2b — Complementary reference clock input 2 |
| Pin 9 | VDD — Core supply |
| Pin 10 | IN3 — Differential reference clock input 3 |
| Pin 11 | IN3b — Complementary reference clock input 3 |
| Pin 12 | GND — Ground |
| Pin 13 | SDA — I2C data / SPI serial data |
| Pin 14 | SCL — I2C clock / SPI clock |
| Pin 15 | CSb — SPI chip select (active low) |
| Pin 16 | INT — Interrupt output (active low, open-drain) |
| Pin 17 | RSTb — Reset (active low) |
| Pin 18 | I2C_SEL — I2C address select |
| Pin 19 | VDDO0 — Output driver supply for OUT0 |
| Pin 20 | OUT0 — Differential output 0 |
| Pin 21 | OUT0b — Complementary differential output 0 |
| Pin 22 | GND — Ground |
| Pin 23 | VDDO1 — Output driver supply for OUT1 |
| Pin 24 | OUT1 — Differential output 1 |
| Pin 25 | OUT1b — Complementary differential output 1 |
| Pin 26 | GND — Ground |
| Pin 27 | VDDO2 — Output driver supply for OUT2 |
| Pin 28 | OUT2 — Differential output 2 |
| Pin 29 | OUT2b — Complementary differential output 2 |
| Pin 30 | GND — Ground |
| Pin 31 | VDDO3 — Output driver supply for OUT3 |
| Pin 32 | OUT3 — Differential output 3 |
| Pin 33 | OUT3b — Complementary differential output 3 |
| Pin 34 | GND — Ground |
| Pin 35 | A0 — I2C address LSB / NC |
| Pin 36 | VDD — Core supply |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | XO — Crystal oscillator interface |
| Pin 39 | XOb — Crystal oscillator interface complement |
| Pin 40 | GND — Ground |
| Pin 41 | NC — Not connected (per datasheet) |
| Pin 42 | NC — Not connected (per datasheet) |
| Pin 43 | NC — Not connected (per datasheet) |
| Pin 44 | VDD — Core supply |
| Pin EP | ePAD — Exposed thermal pad - tie to ground |
Typische Anwendungen
SI5340A-D-GM ist geeignet für 7 Anwendungs: 100G / 400G Ethernet Line-Card Timing, FPGA / ASIC Reference Clock Tree, OTN / SONET / SDH Equipment Timing, Test & Measurement Instrumentation, Broadcast Video / Pro AV Routers, Wireless Baseband / RRH Timing, Industrial / Data Acquisition Timing.
100G / 400G Ethernet Line-Card Timing
The SI5340A-D-GM provides the four reference clocks a 100G/400G Ethernet PHY or switch ASIC needs while keeping phase jitter at 0.09 ps RMS - tight enough to clear the IEEE 802.3 25G/50G SerDes reference-clock mask. Placed adjacent to the PHY, the Si5340A fan-outs one recovered line clock into independent 156.25 MHz, 161.13 MHz, 312.5 MHz, and 644.53 MHz references for the MAC, FEC, retimer, and gearbox domains. Unlike fixed-frequency XO arrays, the Si5340A retargets each output via CBPro without board respin when the line rate changes from 100G to 400G.
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FPGA / ASIC Reference Clock Tree
Modern FPGAs and ASICs need multiple unrelated clock domains (transceiver reference, fabric clock, memory controller, GT-bank reference). The SI5340A-D-GM drives four of these domains from a single 44-QFN part with MultiSynth fractional synthesis, so non-integer ratios like 156.25 MHz from a 19.44 MHz Stratum-3 reference are generated without external VCXOs. The 0.09 ps RMS jitter meets Xilinx GTY/GTM and Intel Arria 10/Stratix 10 reference-clock masks, eliminating the need for per-bank discrete XO buffers. Per-output enable simplifies power-rail sequencing during FPGA configuration.
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OTN / SONET / SDH Equipment Timing
Carrier-grade OTN/SONET/SDH equipment requires holdover and hitless reference switching among multiple input clocks, which the SI5340A-D-GM supports with four reference inputs (LOS detection) and MultiSynth synthesis. When the primary reference fails, the device enters digital holdover with <1 ppm frequency accuracy, keeping line cards within SONET MTIE limits. The four outputs fan-out to OTU2/OTU3 framers, mappers, and overhead processors, each running at a different stratum-related rate (e.g. 155.52 MHz, 622.08 MHz, 2.488 GHz from 19.44 MHz).
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Test & Measurement Instrumentation
Oscilloscopes, signal generators, and spectrum analyzers need low-jitter reference clocks that can be reconfigured by the host MCU for different measurement modes. The SI5340A-D-GM provides four independent low-noise clocks (0.09 ps RMS jitter) to ADC sampling cores, FPGA fabric, and trigger subsystems from one I2C/SPI-programmable part. CBPro integration lets the ATE developer change frequency plans during firmware updates without board rework. The wide 1.71-3.47 V supply tolerance supports both 1.8 V and 2.5 V analog rails common in precision instruments.
Empfohlen
Broadcast Video / Pro AV Routers
Broadcast routers, frame synchronizers, and pro-AV endpoints require multiple sample-rate clocks (e.g. 27 MHz for SD-SDI, 74.25 MHz for 720p HD-SDI, 148.5 MHz for 1080p 3G-SDI, 297 MHz for UHD-SDI) that are mathematically related but not integer multiples of a single reference. The SI5340A-D-GM generates all four rates from a single 27 MHz video reference via MultiSynth fractional synthesis, eliminating discrete VCXO + PLL chains. Hitless reference switching supports seamless genlock across studio reference changes.
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Wireless Baseband / RRH Timing
4G/5G baseband cards and remote radio heads (RRH) require multiple unrelated clocks for LTE CPRI, 5G eCPRI fronthaul, and baseband DSP - often with mixed sample-rate and CPRI-rate outputs. The SI5340A-D-GM provides four MultiSynth outputs, each independently programmable to 122.88 MHz (LTE), 153.6 MHz (5G NR), 184.32 MHz (CPRI-7), and 245.76 MHz (CPRI-8) from a single GPS-disciplined reference. 0.09 ps jitter supports the 30.72 Msps LTE and 61.44 Msps 5G numerologies directly. Holdover mode preserves synchronization during GPS loss.
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Industrial / Data Acquisition Timing
Industrial data acquisition (DAQ) modules and process controllers often combine high-speed ADCs with FPGA post-processing, requiring both a high-frequency ADC sample clock (e.g. 125 MHz) and slower FPGA fabric clocks. The SI5340A-D-GM synthesizes the ADC sample clock and three auxiliary outputs (FPGA fabric, GPIO timing, communication bus) from one crystal reference, reducing BOM and PCB area. The -40 C to +85 C industrial temperature range supports outdoor and factory-floor deployments; per-output enable powers down unused domains.
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Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für SI5340A-D-GM – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | SI5340A-D-GMR | SI5340B-A-GM | SI5340C-B-GMR | SI5341A-B-GMR |
|---|---|---|---|---|---|
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Package | 44-QFN (7x7 mm) | 44-QFN (7x7 mm) | 44-QFN (7x7 mm) | 44-QFN (7x7 mm) | 44-QFN (7x7 mm) |
| Number of Outputs | 4 | 4 | 4 | 4 | 10 |
| Maximum Output Frequency | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz |
| Phase Jitter (12 kHz-20 MHz) | 0.09 ps RMS | 0.09 ps RMS | 0.09 ps RMS | 0.09 ps RMS | 0.09 ps RMS |
| Supply Voltage Range | 1.71 V - 3.47 V | 1.71 V - 3.47 V | 1.71 V - 3.47 V | 1.71 V - 3.47 V | 1.71 V - 3.47 V |
| Number of Reference Inputs | 4 | 4 | 4 | 4 | 4 |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Factory NVM Frequency Plan | -D (default) | -D default | Custom A-plan | Custom B-plan | Custom B-plan, 10 outputs |
Wichtigste Unterscheidungsmerkmale
- MultiSynth fractional synthesis with 0.09 ps RMS jitter (vs. Conventional integer-N PLL clock generators (e.g. CDCE913))
- Four reference inputs with hitless switching and holdover (vs. Single-reference clock generators)
- Same 44-QFN footprint scales to 10 outputs via Si5341 (vs. Larger multi-chip clock tree stacks)
Designhinweise
Estimated: the SI5340A-D-GM core VDD pins (3, 6, 9, 36, 44) each need a 0.1 uF X7R ceramic decoupling cap placed within 2 mm of the pin, plus a 10 uF bulk cap on the supply plane. Per-output VDDO pins (19, 23, 27, 31) require their own 0.1 uF caps as close as possible. Tie the exposed pad (EP) to a stitched ground plane with at least 16 thermal vias to keep junction temperature rise below 20 C at the 0.3 W typical dissipation.
Route each differential output pair (OUTx/OUTx_b) with 100 ohm differential impedance and matched lengths within 5 mil (0.13 mm) to preserve jitter performance. Keep reference input traces short and surrounded by ground via stitching; place the device at least 3 mm away from any switching regulator to avoid coupling noise into the reference path. The CBPro clock-builder tool generates a complete schematic and layout review checklist specific to the chosen frequency plan - use it before tape-out.
Estimated: do not leave the I2C/SPI pins floating during reset - the device samples I2C_SEL on RSTb release to set the I2C address and bus mode. Always read the Si5341/40 Family Reference Manual before substituting a custom NVM plan; small register mistakes (e.g. wrong MultiSynth integer mode) can degrade jitter by an order of magnitude. Finally, do not assume the -D default plan matches your board - verify each output frequency with a frequency counter at first prototype bring-up.
Compliance-Informationen
RoHS compliant per Skyworks product page; industrial temperature grade (-40 C to +85 C). Not AEC-Q100 qualified - contact Skyworks for automotive-grade variants.
