5CSEBA2U19C6N vs 5CSEBA2U19A7N Vergleich
Detaillierter Direktvergleich von 5CSEBA2U19C6N von Intel und 5CSEBA2U19A7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 5CSEBA2U19C6N | 5CSEBA2U19A7N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $74,60 | $92,10 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 25 K | 25,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Clock Frequency | 925 MHz | — |
| DSP Blocks | Variable-precision DSP | Variable-precision, embedded multiplier/accumulator |
| Gehäuse | 484-pin UBGA (19x19 mm) | 484-UBGA (U19), 19x19 mm |
| Montageart | Surface Mount | Surface Mount (FBGA) |
| Operating Temperature Grade | Commercial (other) | — |
| Memory Interfaces | DDR2, DDR3, LPDDR2 with ECC | — |
| HPS Peripherals | GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC | — |
| L2 Cache | 512 KB shared | — |
| L1 Cache per Core | 32 KB I-cache + 32 KB D-cache | — |
| FPGA-to-HPS Bridges | AXI-32/AXI-64, FPGA-to-SDRAM ports | — |
| Process Technology | TSMC 28 nm low-power | 28 nm low-power |
| RoHS-Status | Compliant | Compliant |
| Device Variant | — | 5CSEA2 (U19 device) |
| HPS Processor | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 700 MHz |
| Core Voltage (VCCINT) | — | 1.1 V |
| Temperature Grade | — | Automotive A7 |
| AEC-Q100 | — | Qualified |
| User I/O Pins | — | 161 |
| Memory | — | Embedded SRAM + DDR3/LPDDR2 controller (HPS) |
| MSL-Level | — | [DATA_NEEDED: MSL level] |
| Lead-Free | — | Yes |