5CSEBA2U19C6N vs 5CSEBA2U19A7N Comparaison
Comparaison détaillée côte à côte de 5CSEBA2U19C6N par Intel et 5CSEBA2U19A7N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 5CSEBA2U19C6N | 5CSEBA2U19A7N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $74,60 | $92,10 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 25 K | 25,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Clock Frequency | 925 MHz | — |
| DSP Blocks | Variable-precision DSP | Variable-precision, embedded multiplier/accumulator |
| Boîtier | 484-pin UBGA (19x19 mm) | 484-UBGA (U19), 19x19 mm |
| Type de montage | Surface Mount | Surface Mount (FBGA) |
| Operating Temperature Grade | Commercial (other) | — |
| Memory Interfaces | DDR2, DDR3, LPDDR2 with ECC | — |
| HPS Peripherals | GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC | — |
| L2 Cache | 512 KB shared | — |
| L1 Cache per Core | 32 KB I-cache + 32 KB D-cache | — |
| FPGA-to-HPS Bridges | AXI-32/AXI-64, FPGA-to-SDRAM ports | — |
| Process Technology | TSMC 28 nm low-power | 28 nm low-power |
| Statut RoHS | Compliant | Compliant |
| Device Variant | — | 5CSEA2 (U19 device) |
| HPS Processor | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 700 MHz |
| Core Voltage (VCCINT) | — | 1.1 V |
| Temperature Grade | — | Automotive A7 |
| AEC-Q100 | — | Qualified |
| User I/O Pins | — | 161 |
| Memory | — | Embedded SRAM + DDR3/LPDDR2 controller (HPS) |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |
| Lead-Free | — | Yes |