5CSEBA2U19C6N vs 5CSEBA2U19A7N Comparación
Comparación detallada lado a lado de 5CSEBA2U19C6N por Intel y 5CSEBA2U19A7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | 5CSEBA2U19C6N | 5CSEBA2U19A7N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $74,60 | $92,10 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 25 K | 25,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Clock Frequency | 925 MHz | — |
| DSP Blocks | Variable-precision DSP | Variable-precision, embedded multiplier/accumulator |
| Encapsulado | 484-pin UBGA (19x19 mm) | 484-UBGA (U19), 19x19 mm |
| Tipo de montaje | Surface Mount | Surface Mount (FBGA) |
| Operating Temperature Grade | Commercial (other) | — |
| Memory Interfaces | DDR2, DDR3, LPDDR2 with ECC | — |
| HPS Peripherals | GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC | — |
| L2 Cache | 512 KB shared | — |
| L1 Cache per Core | 32 KB I-cache + 32 KB D-cache | — |
| FPGA-to-HPS Bridges | AXI-32/AXI-64, FPGA-to-SDRAM ports | — |
| Process Technology | TSMC 28 nm low-power | 28 nm low-power |
| Estado RoHS | Compliant | Compliant |
| Device Variant | — | 5CSEA2 (U19 device) |
| HPS Processor | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 700 MHz |
| Core Voltage (VCCINT) | — | 1.1 V |
| Temperature Grade | — | Automotive A7 |
| AEC-Q100 | — | Qualified |
| User I/O Pins | — | 161 |
| Memory | — | Embedded SRAM + DDR3/LPDDR2 controller (HPS) |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |
| Lead-Free | — | Yes |