5CSEBA4U23C6N vs 5CSEBA4U23I7LN Vergleich
Detaillierter Direktvergleich von 5CSEBA4U23C6N von Intel und 5CSEBA4U23I7LN von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
5CSEBA4U23C6N - Cyclone V SE SoC FPGA 40K LE, Dual ARM Cortex-A9 | Intel
5CSEBA4U23C6N ✓ AktivSpezifikationsvergleich
| Parameter | 5CSEBA4U23C6N | 5CSEBA4U23I7LN |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $86,20 | $99,75 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 40,000 | 40,000 |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count] | — |
| Embedded Memory (M10K + MLAB) | 2,460 Kbits | — |
| DSP Blocks (18x18 Multipliers) | 112 | — |
| HPS Processor Cores | Dual ARM Cortex-A9 MPCore | — |
| HPS Maximum CPU Clock | 925 MHz | — |
| Hard Memory Controller | DDR3 / DDR3L / LPDDR2 | — |
| Process Technology | TSMC 28 nm low-power | 28nm TSMC low-power |
| Core Voltage (VCC) | 1.1 V | — |
| General-Purpose FPGA I/Os | 188 | — |
| Transceivers | Not integrated on SE device | 3.125 Gbps (per Cyclone V family) |
| Gehäuse | 672-pin UFBGA / UBGA, 23 x 23 mm, 0.8 mm pitch | 672-pin UBGA (23x23 mm) |
| Montageart | Surface Mount (BGA) | Surface Mount |
| Betriebs-Sperrschichttemperatur | -40 C to +100 C (typical SE spec; exact C6 grade per datasheet) | — |
| Configuration Modes | JTAG (IEEE 1149.1), Active Serial (AS) via EPCS/EPCQ | — |
| RoHS-Status | Compliant | Compliant |
| Processor Cores | — | Dual ARM Cortex-A9 MPCore |
| Processor Clock Speed | — | 925 MHz |
| Betriebstemperatur | — | -40C to +100C (Industrial) |
| Embedded Memory | — | [DATA_NEEDED: exact embedded memory size in bits] |
| DSP Blocks (18x18 multipliers) | — | [DATA_NEEDED: exact multiplier count] |
| External Memory Interface | — | DDR3, DDR2, LPDDR2 (controller integrated in HPS + soft IP in FPGA fabric) |
| MSL-Level | — | 3 |
| Lead-Free | — | Yes |
| Halogenfrei | — | [DATA_NEEDED] |
| Number of GPIOs | — | [DATA_NEEDED: per device variant] |
| Number of PLLs | — | [DATA_NEEDED: per device variant] |