5M160ZM68A5N vs 5M160ZE64C5N Vergleich
Detaillierter Direktvergleich von 5M160ZM68A5N von Altera und 5M160ZE64C5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 5M160ZM68A5N | 5M160ZE64C5N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $5,10 | $4,95 |
| Family | MAX V | — |
| Device Variant | 5M160Z (128 macrocells, 1.8 V, speed grade -7) | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 4 | — |
| User I/Os | 52 | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Propagation Delay (tPD) | 14 ns | — |
| Standby Current (ICCSTBY) | 25 uA (typical) | — |
| Core Supply Voltage (VCCINT) | 1.8 V (1.71 V to 1.89 V) | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Gehäuse | 68-ball FBGA (FineLine BGA), 0.5 mm pitch | 64-pin EQFP (E64) with exposed pad |
| JEDEC Package Code | S-PBGA-B68 | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| Betriebstemperatur | -40C to +125C (industrial) | 0°C to +85°C (commercial) |
| Programming Interface | IEEE Std 1149.1 JTAG BST | JTAG (IEEE 1149.1) / In-system |
| Automotive Qualification | AEC-Q100 | — |
| RoHS-Status | Compliant | Compliant |
| Series | — | MAX V |
| Device Family | — | MAX V (5M160Z) |
| Logic Elements (LE) | — | 160 |
| User I/O Pins | — | 54 |
| Maximum Operating Frequency (fMAX) | — | 118.3 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 1.4 ns (per datasheet) |
| Configuration Memory | — | Non-volatile Flash |
| Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Bank Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| MSL-Level | — | 3 |