5M160ZM68C5N vs 5M1270ZT144C5N Vergleich
Detaillierter Direktvergleich von 5M160ZM68C5N von Altera und 5M1270ZT144C5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ AktivSpezifikationsvergleich
| Parameter | 5M160ZM68C5N | 5M1270ZT144C5N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3,12 | $12,45 |
| Family | MAX V CPLD | — |
| Series | 5M160Z | MAX V |
| Macrocells | 128 | 980 |
| Logic Elements (typical) | 160 | — |
| Maximum Operating Frequency | 118.3 MHz | — |
| Pin-to-Pin Logic Delay | 7.5 ns | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| User Flash Memory | 8 Kbits | — |
| Core Supply Voltage | 1.8 V | — |
| I/O Standards Supported | LVTTL, LVCMOS 1.5/1.8/2.5/3.3 V | — |
| Package Type | 68-ball Micro FineLine BGA (MBGA) | — |
| Betriebstemperaturbereich | 0C to +85C (commercial) | — |
| Programming Interface | JTAG (IEEE Std. 1149.1), in-system programmable | JTAG in-system programmable (Altera Quartus II) |
| Configuration Memory | Non-volatile flash (instant-on, no boot PROM required) | Flash (non-volatile, in-system programmable) |
| Internal Oscillator | Yes (on-chip) | — |
| RoHS-Status | Compliant | Compliant |
| Lead-Free | Yes | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements | — | 1270 |
| User I/Os | — | 114 |
| Maximum Internal Frequency | — | 118.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 6.2 ns |
| Internal Frequency (typical) | — | 201 MHz |
| User Flash Memory (UFM) | — | 8 Kbits |
| VCCINT (Core Supply) | — | 1.71 V to 1.89 V |
| VCCIO (I/O Supply, per bank) | — | 1.2 V to 3.3 V |
| Number of I/O Banks | — | 4 |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins |
| JTAG Interface | — | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) |
| Program/Erase Cycles | — | Up to 100,000 |
| Gehäuse | — | TQFP-144 (22 x 22 mm, 0.5 mm pitch) |
| Montageart | — | Surface Mount |
| Betriebstemperatur | — | 0 C to +85 C (commercial grade) |