5M160ZM68C5N vs 5M1270ZT144C5N 对比

详细并排对比 5M160ZM68C5N 出自 Altera 和 5M1270ZT144C5N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 5M160ZM68C5N 5M1270ZT144C5N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $3.12 $12.45
Family MAX V CPLD —
Series 5M160Z MAX V
Macrocells 128 980
Logic Elements (typical) 160 —
Maximum Operating Frequency 118.3 MHz —
Pin-to-Pin Logic Delay 7.5 ns —
Number of Logic Array Blocks (LABs) 4 —
User Flash Memory 8 Kbits —
Core Supply Voltage 1.8 V —
I/O Standards Supported LVTTL, LVCMOS 1.5/1.8/2.5/3.3 V —
Package Type 68-ball Micro FineLine BGA (MBGA) —
工作温度范围 0C to +85C (commercial) —
Programming Interface JTAG (IEEE Std. 1149.1), in-system programmable JTAG in-system programmable (Altera Quartus II)
Configuration Memory Non-volatile flash (instant-on, no boot PROM required) Flash (non-volatile, in-system programmable)
Internal Oscillator Yes (on-chip) —
RoHS 状态 Compliant Compliant
Lead-Free Yes —
MSL 等级 [DATA_NEEDED: MSL level] —
Device Type — CPLD (Complex Programmable Logic Device)
Logic Elements — 1270
User I/Os — 114
Maximum Internal Frequency — 118.3 MHz
Pin-to-Pin Propagation Delay (tPD) — 6.2 ns
Internal Frequency (typical) — 201 MHz
User Flash Memory (UFM) — 8 Kbits
VCCINT (Core Supply) — 1.71 V to 1.89 V
VCCIO (I/O Supply, per bank) — 1.2 V to 3.3 V
Number of I/O Banks — 4
Supported I/O Standards — LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins
JTAG Interface — IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1)
Program/Erase Cycles — Up to 100,000
封装 — TQFP-144 (22 x 22 mm, 0.5 mm pitch)
安装类型 — Surface Mount
工作温度 — 0 C to +85 C (commercial grade)

数据手册与资源

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