ADC1213D105HN-C18 vs ADC1213D080HN-C18 Vergleich
Detaillierter Direktvergleich von ADC1213D105HN-C18 von Renesas Electronics und ADC1213D080HN-C18 von Renesas Electronics. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Renesas Electronics
ADC1213D105HN-C18 - Dual 12-bit 105MSPS ADC, JESD204A | Renesas
ADC1213D105HN-C18 ✓ AktivRenesas Electronics
ADC1213D080HN-C18 - 12-bit 80MSPS Dual ADC with JESD204A | Renesas
ADC1213D080HN-C18 ✓ AktivSpezifikationsvergleich
| Parameter | ADC1213D105HN-C18 | ADC1213D080HN-C18 |
|---|---|---|
| Marke | Renesas Electronics | Renesas Electronics |
| Kategorie | ADC/DAC | ADC/DAC |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $39,95 | $21,75 |
| Auflösung | 12 bit | 12 bit |
| Number of Channels | 2 (dual, simultaneous sampling) | 2 (dual, simultaneous sampling) |
| Sampling Rate (per channel) | 105 MSPS | — |
| Sampling Rate (per second) | 105M | — |
| Architecture | Pipelined | Pipelined |
| Data Interface | Serial JESD204A (configurable lanes) | — |
| Input Type | Differential analog inputs | Differential / single-ended (configurable) |
| Number of Inputs | 2 | — |
| Gehäuse | 56-VFQFPN exposed pad (8x8 mm) | 56-VFQFPN exposed pad (8x8 mm) |
| Montageart | Surface Mount | Surface Mount |
| Packaging | Tape & Reel | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant |
| Betriebstemperaturbereich | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (industrial) |
| Versorgungsspannung | [DATA_NEEDED: supply voltage] | — |
| Power Dissipation | [DATA_NEEDED: power dissipation] | — |
| INL (max) | [DATA_NEEDED: INL] | — |
| DNL (max) | [DATA_NEEDED: DNL] | — |
| SNR | [DATA_NEEDED: SNR] | [DATA_NEEDED: SNR dBFS at fIN] |
| SFDR | [DATA_NEEDED: SFDR] | [DATA_NEEDED: SFDR dBc] |
| Sampling Rate per Channel | — | 80 MSPS |
| Data Output Interface | — | JESD204A (serial, up to 3.125 Gbps lane) |
| Analog Supply Voltage (AVDD) | — | 1.8 V |
| Digital/Drive Supply Voltage (DRVDD) | — | 3.3 V |
| Input Bandwidth | — | [DATA_NEEDED: full-power input bandwidth MHz] |
| ENOB | — | [DATA_NEEDED: ENOB bits at fIN] |
| Power Consumption | — | [DATA_NEEDED: power mW per channel at 80 MSPS] |
| Configuration Interface | — | SPI-compatible serial |
| MSL-Level | — | 3 (per JEDEC J-STD-020) |
| Lead-Free | — | Yes |