AT45DB041E-SHN2B-T vs AT25DF081A-SH-B Vergleich
Detaillierter Direktvergleich von AT45DB041E-SHN2B-T von Renesas Electronics und AT25DF081A-SH-B von Renesas Electronics. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Renesas Electronics
AT45DB041E-SHN2B-T - 4Mbit 1.65V SPI DataFlash 85MHz | Renesas
AT45DB041E-SHN2B-T ✓ AktivSpezifikationsvergleich
| Parameter | AT45DB041E-SHN2B-T | AT25DF081A-SH-B |
|---|---|---|
| Marke | Renesas Electronics | Renesas Electronics |
| Kategorie | Memory ICs | Memory ICs |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,92 | $0,58 |
| Speichertyp | NOR Flash (DataFlash, SPI) | Serial NOR Flash |
| Speichergröße | 4 Mbit (512K x 8) plus 128 kbits extra | — |
| Speicherorganisation | 2048 pages x 256 bytes (or 2112 x 264 bytes) | — |
| Supply Voltage (VCC) | 1.65 V to 3.6 V | 2.7 V to 3.6 V |
| Schnittstellentyp | SPI (3-wire: SI, SO, SCK + CS) | — |
| Maximale Taktfrequenz | 85 MHz | 100 MHz |
| Page Size | 256 bytes (or 264 bytes binary page mode) | — |
| SRAM Buffer | Dual, 256/264 bytes | — |
| Betriebstemperatur | -40C to +85C (industrial) | -40C to +85C |
| Gehäuse | 8-SOIC (EIAJ 208mil, 5.23 mm body width) | 8-SOIC (SOIC-W, 208 mil) |
| Montageart | Surface Mount | — |
| Packaging | Tape & Reel | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | Compliant | Compliant |
| Sector Erase Size | 64 KB (4 KB block, 256-byte page erase) | — |
| Standby Current | [DATA_NEEDED: deep power-down typical value] | — |
| Memory Density | — | 8 Mbit (1 Mbyte) |
| Memory Organization | — | 4K x 256 bytes |
| Schnittstelle | — | SPI (Single/Dual), Mode 0 and Mode 3 |
| Sector / Block Erase Sizes | — | 4 KB / 32 KB / 64 KB uniform |
| Page Program Size | — | 1 to 256 bytes |
| Endurance | — | 100,000 erase/program cycles per sector |
| Data Retention | — | >20 years |
| Security Registers | — | Three 256-byte Security Register pages |
| SFDP Support | — | Yes (JEDEC 216 standard) |
| Write Protection | — | Hardware WP pin plus BP0-BP2 status-register bits |