CDK8307AILP64 vs CDK8307BILP64 Vergleich
Detaillierter Direktvergleich von CDK8307AILP64 von MaxLinear und CDK8307BILP64 von MaxLinear. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
MaxLinear
CDK8307AILP64 - 12/13-bit Octal Ultra-Low Power LVDS ADC | MaxLinear
CDK8307AILP64 ✓ AktivSpezifikationsvergleich
| Parameter | CDK8307AILP64 | CDK8307BILP64 |
|---|---|---|
| Marke | MaxLinear | MaxLinear |
| Kategorie | ADC/DAC | ADC/DAC |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,45 | $21,40 |
| Auflösung | 12/13-bit (selectable) | 12-bit or 13-bit (programmable) |
| Number of Channels | 8 (simultaneous sampling) | 8 |
| Sample Rate Range | 20 / 40 / 50 / 65 / 80 MSPS | — |
| Architecture | Pipelined ADC with proprietary core | — |
| Output Interface | Serial LVDS | — |
| Reference | Internal reference (integrated) | Internal (integrated bandgap reference) |
| Versorgungsspannung | [DATA_NEEDED: supply voltage] | [DATA_NEEDED: supply voltage rating] |
| Power Dissipation (Typ) | Ultra-low power (per-channel shutdown) | — |
| Shutdown Modes | Per-channel + full-chip idle (via external pin) | — |
| Control Interface | Serial programming interface (SPI-style) | Serial control interface |
| FPGA Compatibility | Designed to interface with major FPGA vendors | — |
| Gehäuse | 64-pin QFN (ILP64) | 64-pin QFN (LP suffix) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperaturbereich | [DATA_NEEDED: temperature range] | [DATA_NEEDED: operating temperature range] |
| RoHS-Status | Compliant | Compliant |
| Original Brand | Cadeka / Exar (now MaxLinear) | — |
| Product Type | — | Octal Analog-to-Digital Converter (ADC) |
| Sample Rate (per channel) | — | 20 / 40 / 50 / 65 MSPS |
| Total Power Dissipation | — | 280 mW |
| Data Output Interface | — | Serial LVDS |
| Input Type | — | Differential analog inputs (one per channel) |
| Clock Architecture | — | External reference clock with integrated PLL (x12 or x14 multiplication) |