CDK8307AILP64 vs CDK8307BILP64 Comparaison
Comparaison détaillée côte à côte de CDK8307AILP64 par MaxLinear et CDK8307BILP64 par MaxLinear. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
MaxLinear
CDK8307AILP64 - 12/13-bit Octal Ultra-Low Power LVDS ADC | MaxLinear
CDK8307AILP64 ✓ ActifComparaison des spécifications
| Paramètre | CDK8307AILP64 | CDK8307BILP64 |
|---|---|---|
| Marque | MaxLinear | MaxLinear |
| Catégorie | ADC/DAC | ADC/DAC |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $18,45 | $21,40 |
| Résolution | 12/13-bit (selectable) | 12-bit or 13-bit (programmable) |
| Number of Channels | 8 (simultaneous sampling) | 8 |
| Sample Rate Range | 20 / 40 / 50 / 65 / 80 MSPS | — |
| Architecture | Pipelined ADC with proprietary core | — |
| Output Interface | Serial LVDS | — |
| Reference | Internal reference (integrated) | Internal (integrated bandgap reference) |
| Tension d'alimentation | [DATA_NEEDED: supply voltage] | [DATA_NEEDED: supply voltage rating] |
| Power Dissipation (Typ) | Ultra-low power (per-channel shutdown) | — |
| Shutdown Modes | Per-channel + full-chip idle (via external pin) | — |
| Control Interface | Serial programming interface (SPI-style) | Serial control interface |
| FPGA Compatibility | Designed to interface with major FPGA vendors | — |
| Boîtier | 64-pin QFN (ILP64) | 64-pin QFN (LP suffix) |
| Type de montage | Surface Mount | Surface Mount |
| Plage de température de fonctionnement | [DATA_NEEDED: temperature range] | [DATA_NEEDED: operating temperature range] |
| Statut RoHS | Compliant | Compliant |
| Original Brand | Cadeka / Exar (now MaxLinear) | — |
| Product Type | — | Octal Analog-to-Digital Converter (ADC) |
| Sample Rate (per channel) | — | 20 / 40 / 50 / 65 MSPS |
| Total Power Dissipation | — | 280 mW |
| Data Output Interface | — | Serial LVDS |
| Input Type | — | Differential analog inputs (one per channel) |
| Clock Architecture | — | External reference clock with integrated PLL (x12 or x14 multiplication) |