CDK8307AILP64 vs CDK8307BILP64 Comparação
Comparação detalhada lado a lado de CDK8307AILP64 por MaxLinear e CDK8307BILP64 por MaxLinear. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
MaxLinear
CDK8307AILP64 - 12/13-bit Octal Ultra-Low Power LVDS ADC | MaxLinear
CDK8307AILP64 ✓ AtivoComparação de especificações
| Parâmetro | CDK8307AILP64 | CDK8307BILP64 |
|---|---|---|
| Marca | MaxLinear | MaxLinear |
| Categoria | ADC/DAC | ADC/DAC |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $18,45 | $21,40 |
| Resolução | 12/13-bit (selectable) | 12-bit or 13-bit (programmable) |
| Number of Channels | 8 (simultaneous sampling) | 8 |
| Sample Rate Range | 20 / 40 / 50 / 65 / 80 MSPS | — |
| Architecture | Pipelined ADC with proprietary core | — |
| Output Interface | Serial LVDS | — |
| Reference | Internal reference (integrated) | Internal (integrated bandgap reference) |
| Tensão de alimentação | [DATA_NEEDED: supply voltage] | [DATA_NEEDED: supply voltage rating] |
| Power Dissipation (Typ) | Ultra-low power (per-channel shutdown) | — |
| Shutdown Modes | Per-channel + full-chip idle (via external pin) | — |
| Control Interface | Serial programming interface (SPI-style) | Serial control interface |
| FPGA Compatibility | Designed to interface with major FPGA vendors | — |
| Encapsulamento | 64-pin QFN (ILP64) | 64-pin QFN (LP suffix) |
| Tipo de montagem | Surface Mount | Surface Mount |
| Faixa de temperatura de operação | [DATA_NEEDED: temperature range] | [DATA_NEEDED: operating temperature range] |
| Status RoHS | Compliant | Compliant |
| Original Brand | Cadeka / Exar (now MaxLinear) | — |
| Product Type | — | Octal Analog-to-Digital Converter (ADC) |
| Sample Rate (per channel) | — | 20 / 40 / 50 / 65 MSPS |
| Total Power Dissipation | — | 280 mW |
| Data Output Interface | — | Serial LVDS |
| Input Type | — | Differential analog inputs (one per channel) |
| Clock Architecture | — | External reference clock with integrated PLL (x12 or x14 multiplication) |