EP1810GM883B vs EP1810JM-45 Vergleich

Detaillierter Direktvergleich von EP1810GM883B von Altera und EP1810JM-45 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1810GM883B EP1810JM-45
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $125,40 $14,20
Device Family EP1810 (Classic EPLD) Classic EPLD (EP1810 series)
Macrocells 48 48
User Flip-Flops Up to 64 —
Total Inputs 60 —
Dedicated Inputs 12 —
I/O Pins 48 (bidirectional, tri-state) —
Propagation Delay (tPD) 50 ns max —
Supply Voltage (VCC) 4.5 V to 5.5 V 4.5 V to 5.5 V
Technology CMOS, UV-erasable CMOS, UV-EPROM configuration
Betriebstemperatur -55 °C to +125 °C (Military, MIL-STD-883B) -55 C to +125 C (military grade)
Package Type Ceramic Pin Grid Array (PGA), 84 pins JLCC-68 (ceramic J-leaded chip carrier)
Package Designator GM (ceramic PGA) —
Processing Level MIL-STD-883B (Class B) —
Programming Method UV-erasable / Altera programming hardware —
Montageart Through-hole (PGA socket or PCB through-hole) Surface Mount (J-lead)
Lead-Free / RoHS [DATA_NEEDED: lead-free status] —
Logic Family TTL-compatible I/O —
Usable Gates — ~900 gates
Propagation Delay (tpd) — 45 ns (max, -45 speed grade)
Package Code — JM (windowed ceramic, UV-erasable)
Pin-Anzahl — 68
I/O Compatibility — CMOS / TTL
Configuration Method — JEDEC fuse map, EPROM programmer
Programming Technology — UV-erasable EPROM (non-volatile, instant-on)
Logic Type — EPLD / PLD (programmable logic device)
RoHS-Status — [DATA_NEEDED: RoHS status - legacy mil-spec part]
MSL-Level — [DATA_NEEDED: MSL level]

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