EP1810GM883B vs EP1810JM-45 比較
詳細な並列比較: EP1810GM883B メーカー: Altera および EP1810JM-45 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810GM883B | EP1810JM-45 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $125.40 | $14.20 |
| Device Family | EP1810 (Classic EPLD) | Classic EPLD (EP1810 series) |
| Macrocells | 48 | 48 |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 (bidirectional, tri-state) | — |
| Propagation Delay (tPD) | 50 ns max | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Technology | CMOS, UV-erasable | CMOS, UV-EPROM configuration |
| 動作温度 | -55 °C to +125 °C (Military, MIL-STD-883B) | -55 C to +125 C (military grade) |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | JLCC-68 (ceramic J-leaded chip carrier) |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | — |
| 実装タイプ | Through-hole (PGA socket or PCB through-hole) | Surface Mount (J-lead) |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Usable Gates | — | ~900 gates |
| Propagation Delay (tpd) | — | 45 ns (max, -45 speed grade) |
| Package Code | — | JM (windowed ceramic, UV-erasable) |
| ピン数 | — | 68 |
| I/O Compatibility | — | CMOS / TTL |
| Configuration Method | — | JEDEC fuse map, EPROM programmer |
| Programming Technology | — | UV-erasable EPROM (non-volatile, instant-on) |
| Logic Type | — | EPLD / PLD (programmable logic device) |
| RoHS ステータス | — | [DATA_NEEDED: RoHS status - legacy mil-spec part] |
| MSLレベル | — | [DATA_NEEDED: MSL level] |