EP1810JC-25 vs EP1810LC-25T Vergleich
Detaillierter Direktvergleich von EP1810JC-25 von Intel und EP1810LC-25T von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810JC-25 | EP1810LC-25T |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $6,80 | $8,40 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | Altera Classic EP1810 |
| Macrocells | 48 | 48 (4 quadrants x 12 macrocells) |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 16 |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V nominal |
| Betriebstemperatur | -40 °C to 85 °C (industrial, per distributor listings) | 0 °C to +70 °C (commercial) |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | CMOS, UV-erasable / OTP |
| Gehäuse | 28-pin ceramic DIP (J) with quartz window | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| Montageart | Through-hole | Surface Mount |
| Erasure Method | UV light (windowed package) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - confirm with manufacturer] |
| Lebenszyklusstatus | NRND (Not Recommended for New Designs) | — |
| Device Type | — | EPLD (Erasable/OTP Complex PLD) |
| Usable Gates | — | Approx. 900 |
| Bidirectional I/O Pins | — | 48 |
| External Clocks | — | 4 |
| I/O Standard | — | TTL-compatible 5 V |
| Programming Tool | — | Altera MAX+PLUS II / Quartus Classic |