EP1810JC-25 vs EP1810LC-25T 비교
다음의 상세 나란히 비교: EP1810JC-25 제조: Intel 및 EP1810LC-25T 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810JC-25 | EP1810LC-25T |
|---|---|---|
| 브랜드 | Intel | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $6.80 | $8.40 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | Altera Classic EP1810 |
| Macrocells | 48 | 48 (4 quadrants x 12 macrocells) |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 16 |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V nominal |
| 동작 온도 | -40 °C to 85 °C (industrial, per distributor listings) | 0 °C to +70 °C (commercial) |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | CMOS, UV-erasable / OTP |
| 패키지 | 28-pin ceramic DIP (J) with quartz window | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| 실장 유형 | Through-hole | Surface Mount |
| Erasure Method | UV light (windowed package) | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - confirm with manufacturer] |
| 수명 주기 상태 | NRND (Not Recommended for New Designs) | — |
| Device Type | — | EPLD (Erasable/OTP Complex PLD) |
| Usable Gates | — | Approx. 900 |
| Bidirectional I/O Pins | — | 48 |
| External Clocks | — | 4 |
| I/O Standard | — | TTL-compatible 5 V |
| Programming Tool | — | Altera MAX+PLUS II / Quartus Classic |