EP1810JC-35 vs EP1810GC-35AB Vergleich

Detaillierter Direktvergleich von EP1810JC-35 von Intel und EP1810GC-35AB von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1810JC-35 EP1810GC-35AB
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $5,48 $9,95
Device Family Classic EPLD (EP1810) —
Device Type UV-Erasable Complex PLD (UV PLD / CPLD) —
Number of Macrocells 48 48
Propagation Delay (tpd) 35 ns (max) —
Maximale Taktfrequenz [DATA_NEEDED: fmax for this speed grade] —
Process Technology CMOS —
Supply Voltage (Vcc) 5 V (nominal) —
Maximum Supply Voltage 5.25 V (per distributor listing) —
Package Type CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) Pin Grid Array (PGA), ceramic
Number of Terminals 68 —
Terminal Form J-Bend —
Betriebstemperaturbereich 0°C to 70°C (Commercial) —
Temperature Grade Commercial —
Erasure Method UV (quartz-windowed ceramic package) —
RoHS-Status Compliant (per Altera listing) unknown
Lead-Free Status Lead-free (per distributor listing) —
Montageart Surface Mount (J-Lead) —
Logic Architecture Programmable AND/OR array with macrocell outputs —
Product Family — Classic EPLD
Technology — CMOS EPROM
Number of Usable Gates — 1200
Maximum Inputs — 64
Maximum Outputs — 48
Number of I/O Pins — 48
Dedicated Input Pins — 12
Propagation Delay (tPD) — 35 ns
Maximum Toggle Frequency — 62.5 MHz
Supply Voltage (VCC) — 5 V
Betriebstemperatur — [DATA_NEEDED: operating temperature range]
Programming Method — UV-erasable EPROM, in-system via JTAG-like interface

Datenblätter & Ressourcen

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