EP1810JC-35 vs EP1810GC-35AB 对比
详细并排对比 EP1810JC-35 出自 Intel 和 EP1810GC-35AB 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810JC-35 | EP1810GC-35AB |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $5.48 | $9.95 |
| Device Family | Classic EPLD (EP1810) | — |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | — |
| Number of Macrocells | 48 | 48 |
| Propagation Delay (tpd) | 35 ns (max) | — |
| 最大时钟频率 | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | Pin Grid Array (PGA), ceramic |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| 工作温度范围 | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| RoHS 状态 | Compliant (per Altera listing) | unknown |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| 安装类型 | Surface Mount (J-Lead) | — |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Product Family | — | Classic EPLD |
| Technology | — | CMOS EPROM |
| Number of Usable Gates | — | 1200 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Number of I/O Pins | — | 48 |
| Dedicated Input Pins | — | 12 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V |
| 工作温度 | — | [DATA_NEEDED: operating temperature range] |
| Programming Method | — | UV-erasable EPROM, in-system via JTAG-like interface |