EP1810JI-35 vs EP1810JC-45 Vergleich
Detaillierter Direktvergleich von EP1810JI-35 von Intel und EP1810JC-45 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810JI-35 | EP1810JC-45 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,60 | $21,10 |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | 48 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | 12 |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| Gehäuse | 28-pin JLCC (J-leaded ceramic, windowed) | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| Betriebstemperatur | -40C to +85C (Industrial) | — |
| Versorgungsspannung | 5 V (typical classic EPLD) | — |
| Programmability | UV-erase, windowed for lab reprogram | — |
| Montageart | Through-Hole (J-lead) | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Equivalent Gates | — | 2100 gates |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| Maximale Taktfrequenz | — | 33.3 MHz |
| Technology | — | CMOS, UV-erasable |
| Maximum Supply Voltage | — | 5.25 V |
| Pin-Anzahl | — | 68 |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |