EP1810JI-35 vs EP1810JC-45 비교
다음의 상세 나란히 비교: EP1810JI-35 제조: Intel 및 EP1810JC-45 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810JI-35 | EP1810JC-45 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $18.60 | $21.10 |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | 48 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | 12 |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| 패키지 | 28-pin JLCC (J-leaded ceramic, windowed) | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| 동작 온도 | -40C to +85C (Industrial) | — |
| 공급 전압 | 5 V (typical classic EPLD) | — |
| Programmability | UV-erase, windowed for lab reprogram | — |
| 실장 유형 | Through-Hole (J-lead) | Surface Mount |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| MSL 레벨 | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Equivalent Gates | — | 2100 gates |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| 최대 클록 주파수 | — | 33.3 MHz |
| Technology | — | CMOS, UV-erasable |
| Maximum Supply Voltage | — | 5.25 V |
| 핀 수 | — | 68 |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |