EP1810LC-25T vs EP1810LC-25 Vergleich
Detaillierter Direktvergleich von EP1810LC-25T von Intel und EP1810LC-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1810LC-25T | EP1810LC-25 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,40 | $8,40 |
| Family | Altera Classic EP1810 | — |
| Device Type | EPLD (Erasable/OTP Complex PLD) | — |
| Macrocells | 48 (4 quadrants x 12 macrocells) | 48 |
| Usable Gates | Approx. 900 | — |
| Dedicated Inputs | 16 | 12 |
| Bidirectional I/O Pins | 48 | — |
| External Clocks | 4 | — |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Supply Voltage (VCC) | 5 V nominal | 5 V (TTL-compatible) |
| Betriebstemperatur | 0 °C to +70 °C (commercial) | [DATA_NEEDED: temperature grade for LC package] |
| Gehäuse | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Montageart | Surface Mount | Surface Mount |
| Technology | CMOS, UV-erasable / OTP | CMOS EPLD (erasable programmable logic device) |
| I/O Standard | TTL-compatible 5 V | — |
| RoHS-Status | [DATA_NEEDED: RoHS status - confirm with manufacturer] | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] |
| Programming Tool | Altera MAX+PLUS II / Quartus Classic | — |
| Product Family | — | Altera Classic EPLD |
| Part Number | — | EP1810LC-25 |
| I/O Pins | — | 48 |
| External Clock Inputs | — | 4 |
| Operating Mode | — | Turbo-only (no slow-power mode) |
| Package Code | — | LC = 68-pin JLCC |
| Programmable Interconnect | — | Global + Local buses |
| Programming Method | — | Altera Classic programmer + MAX+PLUS II legacy flow |
| Lebenszyklusstatus | — | Obsolete (legacy Altera Classic family) |