EP1810LI-45 vs EP1810LI-25 Vergleich
Detaillierter Direktvergleich von EP1810LI-45 von Rochester Electronics und EP1810LI-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Rochester Electronics
EP1810LI-45 - Classic EPLD, 900 Gates, 48 Macrocells, 45ns, PQCC68 | Rochester Electronics (Altera)
EP1810LI-45 ✓ AktivSpezifikationsvergleich
| Parameter | EP1810LI-45 | EP1810LI-25 |
|---|---|---|
| Marke | Rochester Electronics | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $64,10 | $9,95 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic | Altera Classic EPLD |
| Usable Gates | 900 | 900 |
| Macrocells | 48 | 48 |
| Maximum User I/O | 64 inputs / 48 outputs | — |
| Pin-to-Pin Logic Delay (tPD) | 45 ns | — |
| Counter Frequency (fCNT) | up to 100 MHz | — |
| Setup Time (tSU) | [DATA_NEEDED: setup time] | — |
| Technology | CMOS, UV-erasable EPROM configuration | — |
| Versorgungsspannung | 5 V | — |
| Betriebstemperaturbereich | -40 C to +85 C (Industrial, 'I' suffix) | — |
| Gehäuse | 68-pin PLCC / PQCC68 (J-Lead) | 68-pin PLCC (J68, J-Lead) |
| Logic Blocks | 12 LABs of 4 macrocells each | — |
| Configuration Memory | Non-volatile UV-erasable EPROM | — |
| Programming Method | Altera programming hardware with MAX+PLUS II / legacy tools | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | unknown |
| Manufacturer | Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device), UV-erasable / OTP |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Counter Frequency | — | 40 MHz |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V (nominal 5 V) |
| I/O Pins | — | 48 |
| Dedicated Inputs | — | 12 |
| Global Clock Inputs | — | 4 |
| Interconnect | — | Programmable global and local buses |
| JESD-30 Package Code | — | S-PQCC-J68 |
| Process Technology | — | CMOS |
| Operating Temperature (Industrial 'I' suffix) | — | -40 C to +85 C |
| Programming Mode | — | EPROM/UV-erasable (windowed) and OTP |
| Development Tool | — | Altera MAX+PLUS II |
| Lead-Free Status | — | unknown |