EP1810LI-45 vs EP1810LI-25 对比

详细并排对比 EP1810LI-45 出自 Rochester Electronics 和 EP1810LI-25 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1810LI-45 EP1810LI-25
品牌 Rochester Electronics Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $64.10 $9.95
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic Altera Classic EPLD
Usable Gates 900 900
Macrocells 48 48
Maximum User I/O 64 inputs / 48 outputs —
Pin-to-Pin Logic Delay (tPD) 45 ns —
Counter Frequency (fCNT) up to 100 MHz —
Setup Time (tSU) [DATA_NEEDED: setup time] —
Technology CMOS, UV-erasable EPROM configuration —
电源电压 5 V —
工作温度范围 -40 C to +85 C (Industrial, 'I' suffix) —
封装 68-pin PLCC / PQCC68 (J-Lead) 68-pin PLCC (J68, J-Lead)
Logic Blocks 12 LABs of 4 macrocells each —
Configuration Memory Non-volatile UV-erasable EPROM —
Programming Method Altera programming hardware with MAX+PLUS II / legacy tools —
RoHS 状态 [DATA_NEEDED: RoHS status] unknown
Manufacturer Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) —
Device Type — EPLD (Erasable Programmable Logic Device), UV-erasable / OTP
Propagation Delay (tPD) — 25 ns
Maximum Counter Frequency — 40 MHz
Supply Voltage (VCC) — 4.5 V to 5.5 V (nominal 5 V)
I/O Pins — 48
Dedicated Inputs — 12
Global Clock Inputs — 4
Interconnect — Programmable global and local buses
JESD-30 Package Code — S-PQCC-J68
Process Technology — CMOS
Operating Temperature (Industrial 'I' suffix) — -40 C to +85 C
Programming Mode — EPROM/UV-erasable (windowed) and OTP
Development Tool — Altera MAX+PLUS II
Lead-Free Status — unknown

数据手册与资源

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