EP1K100FC4842N vs EP1K100FI4842 Vergleich
Detaillierter Direktvergleich von EP1K100FC4842N von Altera und EP1K100FI4842 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1K100FC4842N | EP1K100FI4842 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $49,80 | $54,30 |
| Series | ACEX-1K | — |
| Family | ACEX-1K Programmable Logic Device Family | ACEX-1K |
| Typical Gates | 100,000 | — |
| Logic Elements | 4,992 | 4,992 |
| Embedded Memory (EAB) | 49,152 bits | — |
| Number of LABs/CLBs | 624 | — |
| Number of I/O | 333 | — |
| Number of EABs | 12 | 6 |
| Voltage - Core | 2.5 V | — |
| Voltage - I/O | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) | — |
| Speed Grade | -2 | — |
| Betriebstemperatur | 0C to +70C (commercial) | -40C to +85C (Industrial) |
| Gehäuse / Bauform | 484-BBGA | — |
| Montageart | Surface Mount | — |
| Process Technology | 0.18 µm CMOS, SRAM-based | 0.18 um CMOS SRAM |
| JTAG (IEEE 1149.1) | Yes (boundary-scan) | — |
| PCI Compliance | 66 MHz | — |
| Configuration Method | SRAM / passive serial / JTAG | Passive Serial / Byte-Wide Parallel via JTAG |
| System Gates | — | 100,000 |
| Total RAM Bits | — | 49,152 |
| Number of LABs | — | 624 |
| User I/O Pins | — | 333 |
| Gehäuse | — | 484-FBGA (FineLine BGA) |
| Core Voltage | — | 2.5 V |
| I/O Standards | — | MultiVolt (2.5V / 3.3V / 5.0V) |
| Internal Performance | — | up to 250 MHz |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| RoHS-Status | — | Compliant |