EP1S60F1020C6NAA vs EP1S60F1020C6N Vergleich
Detaillierter Direktvergleich von EP1S60F1020C6NAA von Altera und EP1S60F1020C6N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1S60F1020C6NAA | EP1S60F1020C6N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $145,00 | $195,00 |
| Family | Stratix | Stratix (EP1S) |
| Series | EP1S60 | Stratix |
| Logic Elements | 57,120 | — |
| Total RAM Bits | 5,215,104 | — |
| Embedded Multipliers | 192 (18x18) | 773 (18x18) |
| Maximum User I/O Pins | 773 | Per datasheet, package-dependent (F1020 variant) |
| Number of LABs/CLBs | 4,510 | — |
| Number of Logic Cells | 57,120 | — |
| Betriebstemperatur | 0C to +85C (commercial) | 0°C to +85°C (Commercial) |
| Gehäuse | 1020-BBGA (FineLine BGA), 33x33 mm, 1.0 mm pitch | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Process Node | 0.13 µm CMOS | — |
| Voltage - Core | 1.5 V | — |
| Voltage - I/O | 1.5V / 1.8V / 2.5V / 3.3V (MultiVolt) | — |
| Speed Grade | C6 | C6 (mid-tier) |
| Lead-Free / RoHS | Yes (N suffix) | — |
| Configuration Scheme | Passive Serial / Fast Passive Parallel / JTAG | — |
| Number of PLLs | 12 | — |
| Global Clocks | 40 | — |
| Logic Elements (LEs) | — | 57,120 |
| Logic Cells | — | 6,570 blocks (per chipdig datasheet summary) |
| Embedded RAM (Total Bits) | — | 5,215,104 bits |
| Package Type | — | 1020-ball FBGA (FineLine BGA), 33 x 33 mm, 1 mm pitch |
| Logic Family / Process | — | CMOS, 0.13 µm |
| Versorgungsspannung | — | Per datasheet (Stratix Device Handbook Vol. 1) |
| Lead-Free / Pb-Free | — | Yes (suffix 'N') |
| RoHS-Status | — | Compliant (per 'N' suffix) |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |
| Configuration | — | JTAG / Passive Serial / Fast Passive Parallel via MSEL pins |
| PLL Count | — | 12 (per Stratix family datasheet) |
| Memory Block Types | — | TriMatrix (M512, M4K, M-RAM) |