EP1S60F1020C6NAA vs EP1S60F1020C6N Comparaison
Comparaison détaillée côte à côte de EP1S60F1020C6NAA par Altera et EP1S60F1020C6N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1S60F1020C6NAA | EP1S60F1020C6N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $145,00 | $195,00 |
| Family | Stratix | Stratix (EP1S) |
| Series | EP1S60 | Stratix |
| Logic Elements | 57,120 | — |
| Total RAM Bits | 5,215,104 | — |
| Embedded Multipliers | 192 (18x18) | 773 (18x18) |
| Maximum User I/O Pins | 773 | Per datasheet, package-dependent (F1020 variant) |
| Number of LABs/CLBs | 4,510 | — |
| Number of Logic Cells | 57,120 | — |
| Température de fonctionnement | 0C to +85C (commercial) | 0°C to +85°C (Commercial) |
| Boîtier | 1020-BBGA (FineLine BGA), 33x33 mm, 1.0 mm pitch | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Process Node | 0.13 µm CMOS | — |
| Voltage - Core | 1.5 V | — |
| Voltage - I/O | 1.5V / 1.8V / 2.5V / 3.3V (MultiVolt) | — |
| Speed Grade | C6 | C6 (mid-tier) |
| Lead-Free / RoHS | Yes (N suffix) | — |
| Configuration Scheme | Passive Serial / Fast Passive Parallel / JTAG | — |
| Number of PLLs | 12 | — |
| Global Clocks | 40 | — |
| Logic Elements (LEs) | — | 57,120 |
| Logic Cells | — | 6,570 blocks (per chipdig datasheet summary) |
| Embedded RAM (Total Bits) | — | 5,215,104 bits |
| Package Type | — | 1020-ball FBGA (FineLine BGA), 33 x 33 mm, 1 mm pitch |
| Logic Family / Process | — | CMOS, 0.13 µm |
| Tension d'alimentation | — | Per datasheet (Stratix Device Handbook Vol. 1) |
| Lead-Free / Pb-Free | — | Yes (suffix 'N') |
| Statut RoHS | — | Compliant (per 'N' suffix) |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |
| Configuration | — | JTAG / Passive Serial / Fast Passive Parallel via MSEL pins |
| PLL Count | — | 12 (per Stratix family datasheet) |
| Memory Block Types | — | TriMatrix (M512, M4K, M-RAM) |