EP1SGX25CF672C6N vs EP1SGX25DF67216 Vergleich
Detaillierter Direktvergleich von EP1SGX25CF672C6N von Intel und EP1SGX25DF67216 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP1SGX25CF672C6N | EP1SGX25DF67216 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $210,00 | $198,00 |
| Family | Stratix GX | Stratix GX |
| Logic Elements | 25,660 | 25,660 |
| Configurable Logic Blocks (CLBs) | 2,852 | — |
| Logic Array Blocks (LABs) | 2,566 | — |
| Embedded Memory (bits) | 1,944,576 | — |
| Maximum User I/O | 455 | — |
| Process Technology | 130 nm CMOS | — |
| Core Voltage (VCCINT) | 1.5 V | — |
| Speed Grade | -6 (commercial) | — |
| Betriebstemperatur | 0 °C to +85 °C | Industrial, -40C to +100C (I-suffix family) |
| Gehäuse | 672-ball FBGA (FineLine BGA) | 672-ball FineLine BGA (DF672) |
| Package Size | 27 x 27 mm | — |
| Ball Pitch | 1.0 mm | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| RoHS-Status | Compliant | Lead-free / RoHS compliant (per Altera product family documentation) |
| Lead-Free | Yes | — |
| Total RAM Bits | — | 1,944,576 |
| Embedded Multipliers (18x18) | — | [DATA_NEEDED: 18x18 multiplier count] |
| Number of PLLs | — | 4 |
| Number of Transceiver Channels | — | 8 (4 in each of 2 banks) |
| Max Transceiver Data Rate | — | 3.1875 Gbps per channel |
| Min Transceiver Data Rate | — | 500 Mbps |
| Core Supply Voltage | — | 1.5 V |
| Auxiliary Supply Voltage | — | 3.3 V |
| I/O Supply Voltage | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank) |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count for DF672 package] |
| On-Die Termination | — | Yes, 100-ohm differential |
| Pre-emphasis / Equalization | — | Programmable (transmitter pre-emphasis; receiver adaptive equalization) |
| Configuration Schemes | — | Passive serial, fast passive parallel, JTAG, Altera enhanced configuration |