EP1SGX25CF672C6N vs EP1SGX25DF67216 比較

詳細な並列比較: EP1SGX25CF672C6N メーカー: Intel および EP1SGX25DF67216 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EP1SGX25CF672C6N EP1SGX25DF67216
ブランド Intel Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $210.00 $198.00
Family Stratix GX Stratix GX
Logic Elements 25,660 25,660
Configurable Logic Blocks (CLBs) 2,852 —
Logic Array Blocks (LABs) 2,566 —
Embedded Memory (bits) 1,944,576 —
Maximum User I/O 455 —
Process Technology 130 nm CMOS —
Core Voltage (VCCINT) 1.5 V —
Speed Grade -6 (commercial) —
動作温度 0 °C to +85 °C Industrial, -40C to +100C (I-suffix family)
パッケージ 672-ball FBGA (FineLine BGA) 672-ball FineLine BGA (DF672)
Package Size 27 x 27 mm —
Ball Pitch 1.0 mm —
実装タイプ Surface Mount Surface Mount (BGA)
RoHS ステータス Compliant Lead-free / RoHS compliant (per Altera product family documentation)
Lead-Free Yes —
Total RAM Bits — 1,944,576
Embedded Multipliers (18x18) — [DATA_NEEDED: 18x18 multiplier count]
Number of PLLs — 4
Number of Transceiver Channels — 8 (4 in each of 2 banks)
Max Transceiver Data Rate — 3.1875 Gbps per channel
Min Transceiver Data Rate — 500 Mbps
Core Supply Voltage — 1.5 V
Auxiliary Supply Voltage — 3.3 V
I/O Supply Voltage — 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank)
Maximum User I/O Pins — [DATA_NEEDED: user I/O count for DF672 package]
On-Die Termination — Yes, 100-ohm differential
Pre-emphasis / Equalization — Programmable (transmitter pre-emphasis; receiver adaptive equalization)
Configuration Schemes — Passive serial, fast passive parallel, JTAG, Altera enhanced configuration

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