EP1SGX25FG672C7 vs EP1SGX25FG1020C4 Vergleich

Detaillierter Direktvergleich von EP1SGX25FG672C7 von Altera und EP1SGX25FG1020C4 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1SGX25FG672C7 EP1SGX25FG1020C4
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $118,00 $195,00
Family Stratix GX Stratix GX
Series Stratix —
Logic Elements (LE) 25,660 —
Total RAM Bits 1,944,576 bits —
User I/O Pins 455 —
Embedded Transceivers Yes (multi-gigabit, up to 3.125 Gbps) 4 channels
Number of Transceivers [DATA_NEEDED: exact transceiver count] —
PLLs 4 —
Global Clocks 16 —
Gehäuse 672-pin FineLine BGA (FG672) 1020-pin FineLine BGA (FBGA), 1.27 mm pitch
Betriebstemperatur 0C to +85C (commercial, speed grade C7) 0 °C to +85 °C (commercial)
Core Voltage 1.5 V 1.5 V (typical)
Process Technology 0.13 micron 0.13 µm CMOS, SRAM-based
Montageart Surface Mount —
Speed Grade 7 (commercial) C4
Configuration Method SRAM-based, JTAG/AS/PS supported —
RoHS-Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: confirm via manufacturer product page]
Lebenszyklusstatus Obsolete (per Altera/Intel product discontinuance notices) Obsolete / Last-time-buy from authorized distributors
Logic Elements — 25,560 LE
Embedded Memory — 1,920 Kbits
Total RAM Blocks — M-RAM + M4K blocks (per Stratix GX architecture)
DSP Blocks — 10 (DSP blocks)
Maximum User I/O Pins — [DATA_NEEDED: exact pin count from datasheet]
Transceiver Data Rate — 600 Mbps to 3.125 Gbps
Configuration Modes — PS, PPS, PPA, JTAG
Configuration Device Required — Yes — external (EPC16 / EPCS recommended)

Datenblätter & Ressourcen

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