EP1SGX25FG672C7 vs EP1SGX25FG1020C4 对比

详细并排对比 EP1SGX25FG672C7 出自 Altera 和 EP1SGX25FG1020C4 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1SGX25FG672C7 EP1SGX25FG1020C4
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $118.00 $195.00
Family Stratix GX Stratix GX
Series Stratix —
Logic Elements (LE) 25,660 —
Total RAM Bits 1,944,576 bits —
User I/O Pins 455 —
Embedded Transceivers Yes (multi-gigabit, up to 3.125 Gbps) 4 channels
Number of Transceivers [DATA_NEEDED: exact transceiver count] —
PLLs 4 —
Global Clocks 16 —
封装 672-pin FineLine BGA (FG672) 1020-pin FineLine BGA (FBGA), 1.27 mm pitch
工作温度 0C to +85C (commercial, speed grade C7) 0 °C to +85 °C (commercial)
Core Voltage 1.5 V 1.5 V (typical)
Process Technology 0.13 micron 0.13 µm CMOS, SRAM-based
安装类型 Surface Mount —
Speed Grade 7 (commercial) C4
Configuration Method SRAM-based, JTAG/AS/PS supported —
RoHS 状态 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: confirm via manufacturer product page]
生命周期状态 Obsolete (per Altera/Intel product discontinuance notices) Obsolete / Last-time-buy from authorized distributors
Logic Elements — 25,560 LE
Embedded Memory — 1,920 Kbits
Total RAM Blocks — M-RAM + M4K blocks (per Stratix GX architecture)
DSP Blocks — 10 (DSP blocks)
Maximum User I/O Pins — [DATA_NEEDED: exact pin count from datasheet]
Transceiver Data Rate — 600 Mbps to 3.125 Gbps
Configuration Modes — PS, PPS, PPA, JTAG
Configuration Device Required — Yes — external (EPC16 / EPCS recommended)

数据手册与资源

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