EP20K400FI672-3N vs EP20K400FI672-3 Vergleich
Detaillierter Direktvergleich von EP20K400FI672-3N von Altera und EP20K400FI672-3 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP20K400FI672-3N | EP20K400FI672-3 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Unknown | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $195,00 |
| Device Type | CMOS loadable programmable logic device | — |
| Product Family | APEX 20K | — |
| Series | EP20K400 | EP20K400 |
| Propagation Delay | 3.6 ns | 3.6 ns |
| Maximale Taktfrequenz | 833 MHz | 833 MHz |
| User I/O Count | 502 | — |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | 2.375 V to 2.625 V |
| Process Technology | CMOS | CMOS |
| Gehäuse | S-PBGA-B672 | — |
| Terminal Count | 672 terminals | 672 |
| Terminal Pitch | 1.000 mm | 1.000 mm |
| Montageart | Surface mount | Surface Mount |
| Logic Capacity | [DATA_NEEDED: logic capacity] | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| I/O Standard Support | [DATA_NEEDED: supported I/O standards] | — |
| RoHS-Status | unknown | — |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX 20K |
| Logic Elements | — | 16640 |
| Total Gates | — | up to 400000 |
| Embedded RAM | — | 212992 bits |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Supply Voltage (Nominal) | — | 2.5 V |
| Package Type | — | PBGA (Plastic BGA) |
| Package Code | — | S-PBGA-B672 |
| Package Shape | — | Square BGA |
| Configuration Interface | — | JTAG (IEEE 1149.1) |
| MSL-Level | — | 3 |
| Peak Reflow Temperature | — | 220 C |