EP20K400FI672-3N vs EP20K400FI672-3 比較
詳細な並列比較: EP20K400FI672-3N メーカー: Altera および EP20K400FI672-3 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K400FI672-3N | EP20K400FI672-3 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Unknown | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $195.00 |
| Device Type | CMOS loadable programmable logic device | — |
| Product Family | APEX 20K | — |
| Series | EP20K400 | EP20K400 |
| Propagation Delay | 3.6 ns | 3.6 ns |
| 最大クロック周波数 | 833 MHz | 833 MHz |
| User I/O Count | 502 | — |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | 2.375 V to 2.625 V |
| Process Technology | CMOS | CMOS |
| パッケージ | S-PBGA-B672 | — |
| Terminal Count | 672 terminals | 672 |
| Terminal Pitch | 1.000 mm | 1.000 mm |
| 実装タイプ | Surface mount | Surface Mount |
| Logic Capacity | [DATA_NEEDED: logic capacity] | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| I/O Standard Support | [DATA_NEEDED: supported I/O standards] | — |
| RoHS ステータス | unknown | — |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX 20K |
| Logic Elements | — | 16640 |
| Total Gates | — | up to 400000 |
| Embedded RAM | — | 212992 bits |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Supply Voltage (Nominal) | — | 2.5 V |
| Package Type | — | PBGA (Plastic BGA) |
| Package Code | — | S-PBGA-B672 |
| Package Shape | — | Square BGA |
| Configuration Interface | — | JTAG (IEEE 1149.1) |
| MSLレベル | — | 3 |
| Peak Reflow Temperature | — | 220 C |