EP20K400FI672-3V vs EP20K400FC672-3 Vergleich

Detaillierter Direktvergleich von EP20K400FI672-3V von Intel und EP20K400FC672-3 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K400FI672-3V EP20K400FC672-3
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $285,00 $138,00
Family APEX 20K (EP20K400) APEX 20K
Logic Elements 16,640 —
Maximum Gates 400,000 —
Typical Gates [DATA_NEEDED: typical gates value] —
Embedded Memory (bits) 212,992 —
Maximum User I/O 502 —
Dedicated Inputs 6 —
Total User I/O + Dedicated Inputs 496 + 6 (variant dependent) —
Maximale Taktfrequenz 714.2 MHz —
Speed Grade -3 (faster) -3 (commercial fastest)
Core Voltage (VCCINT) 2.5 V nominal (2.375 V to 2.625 V) —
Process Technology 0.18 µm CMOS, 4 metal layers 0.22 µm CMOS
Gehäuse 672-ball FineLine BGA (BBGA), 1.0 mm pitch 672-pin FC-FBGA
Montageart Surface Mount Surface Mount
Programmable via JTAG Yes (IEEE 1149.1) —
Supported I/O Standards LVCMOS, LVTTL, SSTL, GTL+, HSTL —
Configuration Modes JTAG, passive serial, passive parallel —
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Betriebstemperatur -40 °C to +85 °C (industrial) 0 °C to 85 °C
MSL-Level [DATA_NEEDED: MSL rating] —
Device Logic Elements — 16,640 cells
Typical Gate Count — 400,000 system gates
Maximum User I/Os — 502
Propagation Delay — 2.5 ns
Internal Performance — 167 MHz
Core Supply Voltage — 2.5 V
Logic Family — CMOS, SRAM-based
Package Code — BGA
Number of Terminals — 672
Terminal Form — Ball (BGA)
Architecture — MultiCore (LUT + Embedded System Blocks)
Programming Method — SRAM, JTAG (ByteBlaster)
Lebenszyklusstatus — Obsolete / Legacy

Datenblätter & Ressourcen

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