EP20K400FI672-3V vs EP20K400FC672-3 对比
详细并排对比 EP20K400FI672-3V 出自 Intel 和 EP20K400FC672-3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K400FI672-3V | EP20K400FC672-3 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $285.00 | $138.00 |
| Family | APEX 20K (EP20K400) | APEX 20K |
| Logic Elements | 16,640 | — |
| Maximum Gates | 400,000 | — |
| Typical Gates | [DATA_NEEDED: typical gates value] | — |
| Embedded Memory (bits) | 212,992 | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 6 | — |
| Total User I/O + Dedicated Inputs | 496 + 6 (variant dependent) | — |
| 最大时钟频率 | 714.2 MHz | — |
| Speed Grade | -3 (faster) | -3 (commercial fastest) |
| Core Voltage (VCCINT) | 2.5 V nominal (2.375 V to 2.625 V) | — |
| Process Technology | 0.18 µm CMOS, 4 metal layers | 0.22 µm CMOS |
| 封装 | 672-ball FineLine BGA (BBGA), 1.0 mm pitch | 672-pin FC-FBGA |
| 安装类型 | Surface Mount | Surface Mount |
| Programmable via JTAG | Yes (IEEE 1149.1) | — |
| Supported I/O Standards | LVCMOS, LVTTL, SSTL, GTL+, HSTL | — |
| Configuration Modes | JTAG, passive serial, passive parallel | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| 工作温度 | -40 °C to +85 °C (industrial) | 0 °C to 85 °C |
| MSL 等级 | [DATA_NEEDED: MSL rating] | — |
| Device Logic Elements | — | 16,640 cells |
| Typical Gate Count | — | 400,000 system gates |
| Maximum User I/Os | — | 502 |
| Propagation Delay | — | 2.5 ns |
| Internal Performance | — | 167 MHz |
| Core Supply Voltage | — | 2.5 V |
| Logic Family | — | CMOS, SRAM-based |
| Package Code | — | BGA |
| Number of Terminals | — | 672 |
| Terminal Form | — | Ball (BGA) |
| Architecture | — | MultiCore (LUT + Embedded System Blocks) |
| Programming Method | — | SRAM, JTAG (ByteBlaster) |
| 生命周期状态 | — | Obsolete / Legacy |