EP20K400GC655-1X vs EP20K400GC655-1 Vergleich
Detaillierter Direktvergleich von EP20K400GC655-1X von Altera und EP20K400GC655-1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpezifikationsvergleich
| Parameter | EP20K400GC655-1X | EP20K400GC655-1 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $193,04 | $135,00 |
| Product Family | Altera APEX 20K | — |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Technology | CMOS | — |
| Gate Count | 400K gates | — |
| Logic Elements | 16640 cells | 16,640 |
| Maximum System Frequency | 250 MHz | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 2.5 V / 3.3 V | 3.3 V |
| Number of User I/O | 496 | — |
| Number of Dedicated Inputs | 6 | — |
| Number of Terminals | 655 | — |
| Package Type | CPGA-655 (Ceramic Pin Grid Array) | — |
| Package Body Material | Ceramic | — |
| Process Technology | 0.22 um | 0.22 µm CMOS |
| Betriebstemperaturbereich | [DATA_NEEDED: operating temperature range] | — |
| Embedded RAM Bits | [DATA_NEEDED: embedded RAM bits] | — |
| RoHS-Status | unknown | Non-compliant (contains lead in ceramic package) |
| Family | — | APEX 20K |
| Series | — | EP20K400 |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Total RAM Bits | — | 212,992 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Maximum Internal Frequency | — | 250 MHz |
| Gehäuse | — | 655-pin CPGA (Ceramic Pin Grid Array) |
| Pin-Anzahl | — | 655 |
| Montageart | — | Through-Hole |
| Betriebstemperatur | — | 0 °C to +85 °C (commercial) |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |