EP20K400GC655-1X vs EP20K400GC655-1 Comparaison
Comparaison détaillée côte à côte de EP20K400GC655-1X par Altera et EP20K400GC655-1 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteComparaison des spécifications
| Paramètre | EP20K400GC655-1X | EP20K400GC655-1 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $193,04 | $135,00 |
| Product Family | Altera APEX 20K | — |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Technology | CMOS | — |
| Gate Count | 400K gates | — |
| Logic Elements | 16640 cells | 16,640 |
| Maximum System Frequency | 250 MHz | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 2.5 V / 3.3 V | 3.3 V |
| Number of User I/O | 496 | — |
| Number of Dedicated Inputs | 6 | — |
| Number of Terminals | 655 | — |
| Package Type | CPGA-655 (Ceramic Pin Grid Array) | — |
| Package Body Material | Ceramic | — |
| Process Technology | 0.22 um | 0.22 µm CMOS |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Embedded RAM Bits | [DATA_NEEDED: embedded RAM bits] | — |
| Statut RoHS | unknown | Non-compliant (contains lead in ceramic package) |
| Family | — | APEX 20K |
| Series | — | EP20K400 |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Total RAM Bits | — | 212,992 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Maximum Internal Frequency | — | 250 MHz |
| Boîtier | — | 655-pin CPGA (Ceramic Pin Grid Array) |
| Nombre de broches | — | 655 |
| Type de montage | — | Through-Hole |
| Température de fonctionnement | — | 0 °C to +85 °C (commercial) |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |