EP20K400GC655-1X vs EP20K400GC655-1 Comparison

Detailed side-by-side comparison of EP20K400GC655-1X by Altera and EP20K400GC655-1 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP20K400GC655-1X EP20K400GC655-1X - 400K-Gate APEX 20K FPGA | Altera

EP20K400GC655-1X - 400K-Gate APEX 20K FPGA | Altera

EP20K400GC655-1X Obsolete

Specification Comparison

Parameter EP20K400GC655-1X EP20K400GC655-1
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Product Family Altera APEX 20K —
Device Type Field Programmable Gate Array (FPGA) —
Technology CMOS —
Gate Count 400K gates —
Logic Elements 16640 cells 16,640
Maximum System Frequency 250 MHz —
Propagation Delay 2.5 ns 2.5 ns
Core Supply Voltage 2.5 V 2.5 V
I/O Supply Voltage 2.5 V / 3.3 V 3.3 V
Number of User I/O 496 —
Number of Dedicated Inputs 6 —
Number of Terminals 655 —
Package Type CPGA-655 (Ceramic Pin Grid Array) —
Package Body Material Ceramic —
Process Technology 0.22 um 0.22 µm CMOS
Operating Temperature Range [DATA_NEEDED: operating temperature range] —
Embedded RAM Bits [DATA_NEEDED: embedded RAM bits] —
RoHS Status unknown Non-compliant (contains lead in ceramic package)
Family — APEX 20K
Series — EP20K400
Maximum Gates — 1,052,000
Typical Gates — 400,000
Embedded System Blocks (ESBs) — 4
Total RAM Bits — 212,992
Maximum User I/O — 502
Dedicated Inputs — 6
Maximum Internal Frequency — 250 MHz
Package — 655-pin CPGA (Ceramic Pin Grid Array)
Pin Count — 655
Mounting Type — Through-Hole
Operating Temperature — 0 °C to +85 °C (commercial)
Configuration Modes — Passive Serial, Passive Parallel Async, Passive Parallel Sync
Boundary Scan — IEEE 1149.1 (JTAG)

Datasheets & Resources

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