EP20K600CB652C9 vs EP20K600CB652C9N Vergleich

Detaillierter Direktvergleich von EP20K600CB652C9 von Altera und EP20K600CB652C9N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K600CB652C9 EP20K600CB652C9N
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $142,50 $128,00
Family APEX 20KC APEX 20KC
Logic Elements / Cells 24,320 —
Number of LABs / CLBs 2,432 —
System Gates 1,537,000 —
Total RAM Bits 311,296 —
User I/O 488 —
Number of I/O Banks [DATA_NEEDED: I/O bank count] —
Versorgungsspannung 1.71 V to 1.89 V —
Process Technology 0.15 µm all-layer copper CMOS 0.15 micron all-layer copper CMOS
Internal Datapath Frequency up to 250 MHz —
Propagation Delay (typ.) 1.48 ns —
Betriebstemperatur 0 °C to 85 °C (commercial) 0 C to 85 C (commercial)
Gehäuse 652-BGA (45 × 45 mm, 1.27 mm pitch) BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch)
Montageart Surface Mount (BGA) Surface Mount (BGA)
Configuration JTAG IEEE 1149.1 / serial / EPC2-compatible —
RoHS-Status Compliant (per Altera product page) [DATA_NEEDED: rohs status]
Product Status Obsolete (per distributor listings) —
Device Type — Loadable PLD (FPGA)
Typical Gates — 600,000
Logic Elements — 24,320
Maximum User I/O — 488
Core Supply Voltage — 1.8 V
Speed Grade — C9 (~1.48 ns propagation delay)
Architecture — MultiCore LUT + embedded system memory (ESB)
On-chip Memory — Embedded system memory blocks (dual-port RAM, FIFO)
Configuration Interface — JTAG (IEEE 1149.1) and serial/PROM configuration
Pin/Pin Compatibility — Pin-compatible with APEX 20KE devices of same package
Toolchain — Altera/Intel Quartus II (legacy APEX support)
MSL-Level — [DATA_NEEDED: MSL level]

Datenblätter & Ressourcen

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