EP20K600CF672-3 vs EP20K600CB672C7 Vergleich

Detaillierter Direktvergleich von EP20K600CF672-3 von Intel und EP20K600CB672C7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP20K600CF672-3 EP20K600CB672C7
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $99,50 $182,50
Family APEX 20KC APEX 20KC
Typical Gates 600,000 600,000
Maximum System Gates 2,432,000 1,053,840
Maximum Logic Elements 2,432 —
Embedded System Memory 311,040 bits (380 Kbits ESB) —
User I/O Pins 488 —
Gehäuse 672-ball FineLine BGA 672-ball FineLine BGA (45 x 45 mm, 1.27 mm pitch)
Speed Grade -3 C7 (commercial, 0 °C to 85 °C)
Process Technology 0.18 µm CMOS 0.15 µm all-layer copper-metal CMOS
PLLs 4 —
Maximum Internal Frequency 180 MHz (per APEX 20K family datasheet) —
Configuration Modes PS, PPS, PPA, JTAG, EPC2/EPC16 —
I/O Standards Supported LVTTL, LVCMOS, SSTL-2/3, HSTL, LVDS, PCI —
Montageart Surface Mount —
Betriebstemperatur [DATA_NEEDED: operating temperature range] 0 °C to 85 °C (commercial)
RoHS-Status Lead-free / RoHS compliant (per Alibaba listing) Compliant
Device Type — FPGA / Programmable Logic Device (PLD)
Logic Elements — 30,960 (typical)
Embedded Memory — 311 kbits (EAB-based)
User I/Os — 488
Propagation Delay — 1.48 ns
Core Voltage — 2.5 V
I/O Voltage Support — 1.8 V, 2.5 V, 3.3 V (MultiVolt I/O)
Number of PLLs — 4
Dual-Port RAM — Yes (4.5 ns access)
Supported I/O Standards — LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, AGP, HSTL, CTT
Configuration Method — EPC configuration devices / JTAG / passive serial

Datenblätter & Ressourcen

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