EP20K60ETC144-2N vs EP20K60EFC144-2XN Vergleich
Detaillierter Direktvergleich von EP20K60ETC144-2N von Intel und EP20K60EFC144-2XN von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K60EFC144-2XN - APEX-20KE FPGA 60K Gates 93 I/O 144-BGA | Intel/Altera
EP20K60EFC144-2XN NrndSpezifikationsvergleich
| Parameter | EP20K60ETC144-2N | EP20K60EFC144-2XN |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $65,00 | $152,00 |
| Family | APEX-20KE | APEX-20K (MultiCore Architecture) |
| Logic Elements | 2,560 | — |
| Typical Gates | 60,000 | — |
| Embedded Memory (ESB) | 32,768 bits (32 Kbits) | — |
| User I/Os | 92 | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Speed Grade | -2 | -2 (per MPN suffix) |
| Internal Frequency (max) | 160 MHz | — |
| Propagation Delay | 1.72 ns | — |
| Process Technology | 0.22 µm CMOS | — |
| Gehäuse | 144-pin TQFP (20 × 20 mm, 0.5 mm pitch) | — |
| Betriebstemperatur | 0 °C to 85 °C (commercial) | — |
| Montageart | Surface Mount | Surface Mount |
| Logic Family | CMOS | CMOS, SRAM-based LUT |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Series | — | APEX-20KE |
| Typical Gate Count | — | 60,000 gates |
| Logic Elements / Embedded Array Blocks | — | 2,560 |
| Embedded Memory (Bits) | — | 32,768 |
| Maximum User I/O | — | 93 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO range] |
| Package Type | — | 144-BGA (Fine-pitch Ball Grid Array) |
| Package Code (per MPN suffix) | — | FBGA / LBGA, 13x13 mm |
| Operating Temperature (TJ) | — | 0 C to +85 C (commercial) |
| Configuration Method | — | JTAG (IEEE 1149.1), Passive Serial, Parallel |