EP20K60ETC144-2N vs EP20K60EFC144-2XN Comparaison
Comparaison détaillée côte à côte de EP20K60ETC144-2N par Intel et EP20K60EFC144-2XN par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP20K60EFC144-2XN - APEX-20KE FPGA 60K Gates 93 I/O 144-BGA | Intel/Altera
EP20K60EFC144-2XN NrndComparaison des spécifications
| Paramètre | EP20K60ETC144-2N | EP20K60EFC144-2XN |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $65,00 | $152,00 |
| Family | APEX-20KE | APEX-20K (MultiCore Architecture) |
| Logic Elements | 2,560 | — |
| Typical Gates | 60,000 | — |
| Embedded Memory (ESB) | 32,768 bits (32 Kbits) | — |
| User I/Os | 92 | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Speed Grade | -2 | -2 (per MPN suffix) |
| Internal Frequency (max) | 160 MHz | — |
| Propagation Delay | 1.72 ns | — |
| Process Technology | 0.22 µm CMOS | — |
| Boîtier | 144-pin TQFP (20 × 20 mm, 0.5 mm pitch) | — |
| Température de fonctionnement | 0 °C to 85 °C (commercial) | — |
| Type de montage | Surface Mount | Surface Mount |
| Logic Family | CMOS | CMOS, SRAM-based LUT |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Series | — | APEX-20KE |
| Typical Gate Count | — | 60,000 gates |
| Logic Elements / Embedded Array Blocks | — | 2,560 |
| Embedded Memory (Bits) | — | 32,768 |
| Maximum User I/O | — | 93 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO range] |
| Package Type | — | 144-BGA (Fine-pitch Ball Grid Array) |
| Package Code (per MPN suffix) | — | FBGA / LBGA, 13x13 mm |
| Operating Temperature (TJ) | — | 0 C to +85 C (commercial) |
| Configuration Method | — | JTAG (IEEE 1149.1), Passive Serial, Parallel |