EP2A25F672C7 vs EP2A25F672I6 Vergleich

Detaillierter Direktvergleich von EP2A25F672C7 von Altera und EP2A25F672I6 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP2A25F672C7 EP2A25F672I6
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $118,00 $178,00
Product Family APEX II —
Logic Elements 25,000 —
Maximum System Gates 1,650,000 —
Maximum RAM Bits 422,976 —
User I/O Count 492 —
Gehäuse 672-ball FCBGA (FineLine BGA) 672-ball FineLine BGA (FBGA-672)
Process Technology 0.15-um all-layer copper, up to 8 metal layers 0.18 µm CMOS
Supply Voltage (Core) 1.5 V —
LVDS Data Rate 1 Gbps per channel (True-LVDS) —
I/O Standards Supported LVDS, LVPECL, PCML, HyperTransport —
Betriebstemperatur 0C to +85C (Commercial) —
Speed Grade -7 6
Configuration Mode Passive Serial, Passive Parallel, JTAG —
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Embedded System Blocks (ESB) Yes - RAM, ROM, CAM, multiplier support —
Family — APEX II
Logic Elements (typical gates) — 25,000
Fabric Architecture — SRAM-based LUT
Core Voltage — 1.5 V
Configuration Method — External SRAM configuration device (EPC series)
Temperature Grade — Industrial (-40 °C to +100 °C ambient)
Embedded Memory — Embedded System Blocks (ESB), dual-port RAM / CAM
DSP Blocks — MultiCore dedicated multipliers
Boundary Scan — JTAG (IEEE 1149.1) compliant
Clock Management — Dedicated PLL / clock tree circuitry
I/O Bank Count — [DATA_NEEDED: number of user I/O banks]
Lead-Free — [DATA_NEEDED: lead-free status]
MSL-Level — [DATA_NEEDED: moisture sensitivity level]
Montageart — Surface Mount (BGA)

Datenblätter & Ressourcen

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