EP2A25F672C7 vs EP2A25F672I6 对比

详细并排对比 EP2A25F672C7 出自 Altera 和 EP2A25F672I6 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A25F672C7 EP2A25F672I6
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $118.00 $178.00
Product Family APEX II —
Logic Elements 25,000 —
Maximum System Gates 1,650,000 —
Maximum RAM Bits 422,976 —
User I/O Count 492 —
封装 672-ball FCBGA (FineLine BGA) 672-ball FineLine BGA (FBGA-672)
Process Technology 0.15-um all-layer copper, up to 8 metal layers 0.18 µm CMOS
Supply Voltage (Core) 1.5 V —
LVDS Data Rate 1 Gbps per channel (True-LVDS) —
I/O Standards Supported LVDS, LVPECL, PCML, HyperTransport —
工作温度 0C to +85C (Commercial) —
Speed Grade -7 6
Configuration Mode Passive Serial, Passive Parallel, JTAG —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Embedded System Blocks (ESB) Yes - RAM, ROM, CAM, multiplier support —
Family — APEX II
Logic Elements (typical gates) — 25,000
Fabric Architecture — SRAM-based LUT
Core Voltage — 1.5 V
Configuration Method — External SRAM configuration device (EPC series)
Temperature Grade — Industrial (-40 °C to +100 °C ambient)
Embedded Memory — Embedded System Blocks (ESB), dual-port RAM / CAM
DSP Blocks — MultiCore dedicated multipliers
Boundary Scan — JTAG (IEEE 1149.1) compliant
Clock Management — Dedicated PLL / clock tree circuitry
I/O Bank Count — [DATA_NEEDED: number of user I/O banks]
Lead-Free — [DATA_NEEDED: lead-free status]
MSL 等级 — [DATA_NEEDED: moisture sensitivity level]
安装类型 — Surface Mount (BGA)

数据手册与资源

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