EP2A25F672C7N vs EP2A25B652C7 Vergleich

Detaillierter Direktvergleich von EP2A25F672C7N von Altera und EP2A25B652C7 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP2A25F672C7N EP2A25B652C7
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $195,00 $285,00
Family APEX II APEX II
Logic Elements 24,320 cells Approximately 25,000 LE
System Gates Approximately 900,000 —
User I/Os 492 —
Propagation Delay (tPD) 1.69 ns —
Internal Operating Frequency Up to 500 MHz —
Core Voltage (VCCINT) 1.5 V —
Process Technology 0.15 µm all-layer copper (up to 8 metal layers) —
Logic Family CMOS —
Package Type 672-ball FC-FBGA (FineLine BGA) —
Package Body Size 27 x 27 mm —
Ball Pitch 1.0 mm —
Betriebstemperatur 0 °C to 85 °C (commercial) Commercial 0C to +85C
High-Speed I/O Support True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps —
Programmable Logic Type Loadable PLD (in-system programmable) —
Embedded Memory Embedded System Blocks (ESB) configurable as dual-port RAM/ROM —
PLLs Up to 4 4
Montageart Surface Mount —
RoHS-Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Embedded System Blocks (ESBs) — [DATA_NEEDED: ESB count]
Maximum User I/O Pins — 488
Gehäuse — 652-ball FineLine BGA
Speed Grade — -7
Core Voltage — 1.5 V
I/O Bank Voltage — 1.5 V / 1.8 V / 2.5 V / 3.3 V
RAM Bits (approx.) — 40,960
Supported I/O Standards — LVTTL, LVCMOS, SSTL, LVDS
Configuration Method — JTAG / Passive Serial / Active Serial
Boundary Scan — IEEE 1149.1 compliant
Design Software — Quartus II

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