EP2A25F672C9ES vs EP2A15F672C9 Vergleich
Detaillierter Direktvergleich von EP2A25F672C9ES von Intel und EP2A15F672C9 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP2A25F672C9ES - APEX II FPGA 900K Gates 236MHz | Intel
EP2A25F672C9ES ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP2A25F672C9ES | EP2A15F672C9 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $122,00 | $175,00 |
| Family | APEX II | — |
| Logic Elements | 24,320 | 16640 |
| System Gates | 900,000 | — |
| Maximum Operating Frequency | 236 MHz | — |
| Propagation Delay | 1.69 ns | 1.94 ns |
| Process Technology | 0.15 µm CMOS (up to 8 metal layers, all-layer copper) | 0.15 µm all-layer copper (up to 8 metal layers) |
| Core Supply Voltage | 1.5 V | 1.5 V |
| User I/Os | 492 | — |
| Gehäuse | 672-pin FC-FBGA (FineLine BGA), 27 x 27 mm, 1.0 mm pitch | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) |
| Speed Grade | -9 | — |
| Configuration Class | ES (Enhanced) | — |
| Betriebstemperatur | 0 °C to 85 °C (Commercial) | 0 °C to 85 °C (commercial) |
| Montageart | Surface Mount | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | — |
| MSL-Level | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Logic Family | CMOS | APEX II (CMOS) |
| Usable Gates | — | 600 K |
| Macrocells | — | 1664 |
| Maximum User I/Os | — | 492 |
| I/O Supply Voltage | — | 3.3 V |
| Maximum Internal Frequency | — | 379 MHz |
| High-Speed I/O Support | — | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps |
| Embedded Memory | — | ESB dual-port RAM / FIFO |
| Configuration Interface | — | Passive serial / Active serial / JTAG (IEEE 1149.1) |
| PLLs | — | On-chip PLLs for clock synthesis and deskew |
| Compliance | — | RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan |