EP2A25F672C9ES vs EP2A15F672C9 对比

详细并排对比 EP2A25F672C9ES 出自 Intel 和 EP2A15F672C9 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Intel
EP2A25F672C9ES EP2A25F672C9ES - APEX II FPGA 900K Gates 236MHz | Intel

EP2A25F672C9ES - APEX II FPGA 900K Gates 236MHz | Intel

EP2A25F672C9ES ⚠ 最后一次采购

规格对比

参数 EP2A25F672C9ES EP2A15F672C9
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $122.00 $175.00
Family APEX II —
Logic Elements 24,320 16640
System Gates 900,000 —
Maximum Operating Frequency 236 MHz —
Propagation Delay 1.69 ns 1.94 ns
Process Technology 0.15 µm CMOS (up to 8 metal layers, all-layer copper) 0.15 µm all-layer copper (up to 8 metal layers)
Core Supply Voltage 1.5 V 1.5 V
User I/Os 492 —
封装 672-pin FC-FBGA (FineLine BGA), 27 x 27 mm, 1.0 mm pitch 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine)
Speed Grade -9 —
Configuration Class ES (Enhanced) —
工作温度 0 °C to 85 °C (Commercial) 0 °C to 85 °C (commercial)
安装类型 Surface Mount —
RoHS 状态 [DATA_NEEDED: RoHS compliance status] —
MSL 等级 [DATA_NEEDED: MSL moisture sensitivity level] —
Logic Family CMOS APEX II (CMOS)
Usable Gates — 600 K
Macrocells — 1664
Maximum User I/Os — 492
I/O Supply Voltage — 3.3 V
Maximum Internal Frequency — 379 MHz
High-Speed I/O Support — True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps
Embedded Memory — ESB dual-port RAM / FIFO
Configuration Interface — Passive serial / Active serial / JTAG (IEEE 1149.1)
PLLs — On-chip PLLs for clock synthesis and deskew
Compliance — RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan

数据手册与资源

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