EP2A25F672C9ES vs EP2A15F672C9 Comparison
Detailed side-by-side comparison of EP2A25F672C9ES by Intel and EP2A15F672C9 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2A25F672C9ES
EP2A25F672C9ES - APEX II FPGA 900K Gates 236MHz | Intel
EP2A25F672C9ES β Last Time BuyAltera
EP2A15F672C9
EP2A15F672C9 - 16,640-Cell APEX II FPGA, 672-FBGA | Intel / Altera
EP2A15F672C9 ObsoleteSpecification Comparison
| Parameter | EP2A25F672C9ES | EP2A15F672C9 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $122.00 | $175.00 |
| Family | APEX II | β |
| Logic Elements | 24,320 | 16640 |
| System Gates | 900,000 | β |
| Maximum Operating Frequency | 236 MHz | β |
| Propagation Delay | 1.69 ns | 1.94 ns |
| Process Technology | 0.15 Β΅m CMOS (up to 8 metal layers, all-layer copper) | 0.15 Β΅m all-layer copper (up to 8 metal layers) |
| Core Supply Voltage | 1.5 V | 1.5 V |
| User I/Os | 492 | β |
| Package | 672-pin FC-FBGA (FineLine BGA), 27 x 27 mm, 1.0 mm pitch | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) |
| Speed Grade | -9 | β |
| Configuration Class | ES (Enhanced) | β |
| Operating Temperature | 0 Β°C to 85 Β°C (Commercial) | 0 Β°C to 85 Β°C (commercial) |
| Mounting Type | Surface Mount | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | β |
| MSL Level | [DATA_NEEDED: MSL moisture sensitivity level] | β |
| Logic Family | CMOS | APEX II (CMOS) |
| Usable Gates | β | 600 K |
| Macrocells | β | 1664 |
| Maximum User I/Os | β | 492 |
| I/O Supply Voltage | β | 3.3 V |
| Maximum Internal Frequency | β | 379 MHz |
| High-Speed I/O Support | β | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps |
| Embedded Memory | β | ESB dual-port RAM / FIFO |
| Configuration Interface | β | Passive serial / Active serial / JTAG (IEEE 1149.1) |
| PLLs | β | On-chip PLLs for clock synthesis and deskew |
| Compliance | β | RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan |